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INTEGRATED CIRCUITS
DATA SHEET
SAA6713AH XGA analog input flat panel controller
Product specification Supersedes data of 2002 Jul 16 2004 Apr 05
Philips Semiconductors
Product specification
XGA analog input flat panel controller
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Programming registers Device ID Initialization Clock management Synchronization pulse distribution Interrupt generation Triple analog-to-digital converter Input interface Colour processing RGB mode detection and auto-adjustment Decoupling FIFO Scaling On screen display Colour look-up table Dithering unit Output interface 8 8.1 8.2 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19
SAA6713AH
BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2004 Apr 05
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
1 FEATURES
SAA6713AH
* Integrated triple Analog-to-Digital Converter (ADC) for RGB analog sampling up to 110 MHz * Integrated PLL for dot clock recovery * Integrated composite sync slicer * Integrated sync-on-green separation * Support of Super Extended Graphics Adapter (SXGA) input mode * Independent horizontal and vertical arbitrary ratio up and downscaling * Video mode detection * Auto-adjustment support for sampling phase and frequency, picture alignment and colour alignment * Advanced colour adjustment * Integrated On Screen Display (OSD) controller with predefined and programmable font and bit-mapped graphics, as well as a hardware overlay cursor * 10-bit gamma correction * Support for 6-bit and 8-bit panels by temporal dithering * Freely programmable output timing supports displays of virtually any manufacturer * Directly interfaces row and column drivers (TCON), versatile timing generation * Programmable output pin ordering * Adjustable output pin ordering * High-speed I2C-bus interface up to 3.4 Mbits/s * Event driven interrupt generation for easy interfacing with microcontroller software. 2 GENERAL DESCRIPTION The input section handles incoming data up to SXGA resolution that can be downscaled individually in width and height to fit to the connected panel resolution. Independent horizontal and vertical upscaling with enhanced programmable filter possibilities provides the IC's core functionality of high-quality scaling. Picture quality is further supported by an enhanced colour management including a 10-bit gamma correction function. A sophisticated dithering unit allows the use of low-end 6-bit panels while keeping up the high quality image impression. An advanced OSD generator is integrated with a fixed 12 x 18 ROM font consisting of 179 ANSI characters, 77 Japanese characters, 48 multicolour icons and 48 single colour icons. In addition to these fixed size characters another 112 different border characters can be generated in any desired font size between 8 x 8 and 32 x 32 pixels. Another 38 special characters are provided particularly for multicolour slider icons that can be parametrized in size and style. For higher flexibility of the OSD appearance a downloadable mixed multicolour or single colour font with any programmable character size between 8 x 8 to 32 x 32 pixels and up to four colours per character can be used and displayed together with the predefined ROM characters. A special bitmap organized graphical OSD with up to 16 individual colours allows to include graphic items like company logos, while a double buffered OSD cursor gives the ability to use animated pointers within an on screen menu. The panel timing interface can not only drive today's common timing controller based panel interfaces, but it has also the capability to directly drive the row and column drivers of a panel itself. An adjustable output pin ordering guarantees easy board layout with any type of panel connector. The SAA6713AH represents a fully integrated single-chip solution for low-end monitors, offering both high quality scaling and an advanced OSD generator.
The SAA6713AH is a single input single-chip Thin Film Transistor (TFT) display controller IC with analog VGA standard input capabilities. Additionally, the SAA6713AH includes a wide range of functions for processing and the measurement of incoming RGB data according to the requirements of an XGA TFT display. Covered functions are accurate measurements for the horizontal and vertical input frequencies to determine the incoming video mode and advanced auto-adjustment features that provide all data for a fast and accurate adjustment of frequency, phase and gain settings. The unit is able to generate interrupts for easy interfacing with a system microcontroller with separately maskable interrupt conditions.
2004 Apr 05
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
3 QUICK REFERENCE DATA SYMBOL VDDD(IC) VDDA PARAMETER digital supply voltage for internal core on pins VDDD(IC1) to VDDD(IC9) analog supply voltage on pins VDDA(R), VDDA(G), VDDA(B), VDDA(ADC)(R), VDDA(ADC)(G) and VDDA(ADC)(B) supply voltage for PLL on pins VDD(PLL)(P), VDDD(PLL)(S) and VDDA(PLL)(S) analog supply voltage for input buffer on pin VDDA(IB) external digital pad supply voltage for pins VDDD(EP1) to VDDD(EP10) external analog pad supply voltage for pin VDDA(EP) total supply current input voltage output voltage for TFT port ambient temperature 0 note 1 CONDITIONS MIN. 2.3 2.3 TYP. 2.5 2.5
SAA6713AH
MAX. 2.7 2.7
UNIT V V
VDD(PLL), VDDD(PLL), VDDA(PLL) VDDA(IB) VDDD(EP) VDDA(EP) IDD(tot) Vi Vo Tamb Note
2.3
2.5
2.7
V
2.7 3.0 3.0 -
3.0 3.3 3.3 350
3.3 3.6 3.6 -
V V V mA
LVTTL compatible CMOS compatible - 70 C
1. Pins HSYNC, VSYNC, SDA and SCL are 5 V tolerant inputs. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA6713AH/V1 QFP160 DESCRIPTION plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height VERSION SOT322-2
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CLK VCLK CLOCK GENERATOR: PANEL CLOCK PLL SAMPLE CLOCK PLL PHASE SHIFT syncs HSYNC VSYNC SYNCONGREEN SLICER syncs SYNC SELECTION AND CSYNC DECODER syncs panel clock sample clock configuration data test control signals MODE DETECTION SOGIN
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Philips Semiconductors
CSG4/A1 CSG2/A0 SCL
I2C-BUS INTERFACE
handbook, full pagewidth
XGA analog input flat panel controller
BLOCK DIAGRAM
SDA TRST
TCK TMS
TDI TDO RST INT
JTAG INTERFACE
CONTROL UNIT
SAA6713AH
AUTOADJUSTMENT
control signals panel control signals
5
RIN GIN BIN RBIAS
INPUT INTERFACE 3 x ADC RGB data 3 x 8-bit
RGB data 3 x 8-bit
PCLK, CSG0 to CSG9, INVA, INVB, PWM, OUTEN
DOWNSCALER
DECOUPLING FIFO
UPSCALER
OUTPUT INTERFACE
RGB data 3 x 6-bit or 3 x 8-bit
PA0 to PA7, PB0 to PB7, PC0 to PC7 PD0 to PD7, PE0 to PE7, PF0 to PF7
OSD RGB data 3 x 8-bit
COLOUR LOOK-UP TABLE
DITHERING RGB data 3 x 10-bit RGB data 3 x 6-bit or 3 x 8-bit
RGB data 3 x 6-bit or 3 x 8-bit
MHC277
SAA6713AH
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
XGA analog input flat panel controller
6 PINNING SYMBOL VSSA(BIAS)(B) BIN VDDA(ADC)(B) REF_B VSSA(ADC)(B) VDDA(B) VSSA(B) VDDA(IB) RBIAS VSSA(BIAS)(SOG) SOGIN VSSA(BIAS)(G) GIN VDDA(ADC)(G) REF_G VSSA(ADC)(G) VDDA(G) VSSA(G) VSSA(BIAS)(R) RIN VDDA(ADC)(R) REF_R VSSA(ADC)(R) VDDA(R) VSSA(R) VDDD(IC1) n.c. n.c. VSSD(IC1) n.c. n.c. VDDD(IC2) n.c. n.c. VSSD(IC2) n.c. RESERVED1 VDDD(IC3) VSSD(IC3) n.c. 2004 Apr 05 PIN(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TYPE - A - A - - - - A - A - A - A - - - - A - A - - - - - - - - - - - - - - - - - - blue colour signal input analog supply voltage for ADC; blue channel (2.5 V) blue channel reference input analog supply ground for ADC; blue channel analog supply voltage; blue channel (2.5 V) analog supply ground; blue channel analog supply voltage for input buffers (3.0 V) external bias resistor input analog ground for bias; sync-on-green sync-on-green input analog ground for bias; green channel green colour signal input analog supply voltage for ADC; green channel (2.5 V) green channel reference input analog supply ground for ADC; green channel analog supply voltage; green channel (2.5 V) analog supply ground; green channel analog ground for bias; red channel red colour signal input analog supply voltage for ADC; red channel (2.5 V) red channel reference input analog supply ground for ADC; red channel analog supply voltage; red channel (2.5 V) analog supply ground; red channel internal digital core supply voltage 1 (2.5 V) not connected not connected internal digital core supply ground 1 not connected not connected internal digital core supply voltage 2 (2.5 V) not connected not connected internal digital core supply ground 2 not connected connect with a pull-up resistor of 51 to VDDE (3.3 V) internal digital core supply voltage 3 (2.5 V) internal digital core supply ground 3 not connected 6 DESCRIPTION analog ground for bias; blue channel
SAA6713AH
Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
SYMBOL SDA SCL RESERVED2 RESERVED3 VSSD(IC4) VDDD(IC4) CLK VSSD(EP1) VDDD(EP1) INT RST PCLK CSG0 CSG1 CSG2/A0 VSSD(EP2) VDDD(EP2) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSSD(EP3) VDDD(EP3) PB0 PB1 VSSD(IC5) VDDD(IC5) PB2 PB3 PB4 PB5 PB6 PB7 VSSD(EP4) VDDD(EP4) PC0 2004 Apr 05
PIN(1) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
TYPE I/O I - - - - I - - O I O O O I/O - - I/O I/O I/O I/O I/O I/O I/O I/O - - I/O I/O - - I/O I/O I/O I/O I/O I/O - - I/O serial clock input (I2C-bus)
DESCRIPTION serial data input or output (I2C-bus) connect with a pull-up resistor of 4.7 k to VDDE (3.3 or 5 V) connect with a pull-up resistor of 4.7 k to VDDE (3.3 or 5 V) internal digital core supply ground 4 internal digital core supply voltage 4 (2.5 V) master clock input external digital pad supply ground 1 external digital pad supply voltage 1 (3.3 V) microcontroller interrupt output (active LOW) master reset input (active LOW) panel clock output control signal generator 0 output control signal generator 1 output control signal generator 2 output (CSG2) or I2C-bus slave address input, latched via hardware reset (A0) external digital pad supply ground 2 external digital pad supply voltage 2 (3.3 V) panel data port A bit 0 panel data port A bit 1 panel data port A bit 2 panel data port A bit 3 panel data port A bit 4 panel data port A bit 5 panel data port A bit 6 panel data port A bit 7 external digital pad supply ground 3 external digital pad supply voltage 3 (3.3 V) panel data port B bit 0 panel data port B bit 1 internal digital core supply ground 5 internal digital core supply voltage 5 (2.5 V) panel data port B bit 2 panel data port B bit 3 panel data port B bit 4 panel data port B bit 5 panel data port B bit 6 panel data port B bit 7 external digital pad supply ground 4 external digital pad supply voltage 4 (3.3 V) panel data port C bit 0 7
Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
SYMBOL PC1 PC2 PC3 PC4 PC5 PC6 PC7 VSSD(EP5) VDDD(EP5) VSSD(IC6) VDDD(IC6) PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VSSD(EP6) VDDD(EP6) VSSD(IC7) VDDD(IC7) PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VSSD(EP7) VDDD(EP7) PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 2004 Apr 05
PIN(1) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
TYPE I/O I/O I/O I/O I/O I/O I/O - - - - O O O O O O O O - - - - O O O O O O O O - - O O O O O O O O panel data port C bit 1 panel data port C bit 2 panel data port C bit 3 panel data port C bit 4 panel data port C bit 5 panel data port C bit 6 panel data port C bit 7
DESCRIPTION
external digital pad supply ground 5 external digital pad supply voltage 5 (3.3 V) internal digital core supply ground 6 internal digital core supply voltage 6 (2.5 V) panel data port D bit 0 panel data port D bit 1 panel data port D bit 2 panel data port D bit 3 panel data port D bit 4 panel data port D bit 5 panel data port D bit 6 panel data port D bit 7 external digital pad supply ground 6 external digital pad supply voltage 6 (3.3 V) internal digital core supply ground 7 internal digital core supply voltage 7 (2.5 V) panel data port E bit 0 panel data port E bit 1 panel data port E bit 2 panel data port E bit 3 panel data port E bit 4 panel data port E bit 5 panel data port E bit 6 panel data port E bit 7 external digital pad supply ground 7 external digital pad supply voltage 7 (3.3 V) panel data port F bit 0 panel data port F bit 1 panel data port F bit 2 panel data port F bit 3 panel data port F bit 4 panel data port F bit 5 panel data port F bit 6 panel data port F bit 7 8
Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
SYMBOL VSSD(IC8) VDDD(IC8) VSSD(EP8) VDDD(EP8) CSG3 CSG4/A1 CSG5 CSG6 CSG7 VSSD(EP9) VDDD(EP9) CSG8 CSG9 VCLK INVA INVB OUTEN PWM VSYNC HSYNC VSSD(EP10) VDDD(EP10) VSSD(IC9) VDDD(IC9) VSS(PLL)(P) VDD(PLL)(P) n.c. VSSA(PLL)(S) VDDA(PLL)(S) VSSD(PLL)(S) VDDD(PLL)(S) TRST TCK TDI TMS TDO
PIN(1) 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157
TYPE - - - - O I/O O O O - - O O I/O O O O O I/O I - - - - - - - - - - - I I I I O
DESCRIPTION internal digital core supply ground 8 internal digital core supply voltage 8 (2.5 V) external digital pad supply ground 8 external digital pad supply voltage 8 (3.3 V) control signal generator 3 output control signal generator 4 output (CSG4) or I2C-bus slave address input, latched via hardware reset (A1) control signal generator 5 output control signal generator 6 output control signal generator 7 output external digital pad supply ground 9 external digital pad supply voltage 9 (3.3 V) control signal generator 8 output control signal generator 9 output sample clock input or output; configurable as output if generated internally data inversion output of ports A, B and C data inversion output of ports D, E and F output enable status output pulse width modulation for control of backlight brightness output vertical sync input or output; configurable as output if decoded from composite sync horizontal and composite sync input external digital pad supply ground 10 external digital pad supply voltage 10 (3.3 V) internal digital core supply ground 9 internal digital core supply voltage 9 (2.5 V) supply ground for panel clock phase locked loop supply voltage for panel clock phase locked loop (2.5 V) do not connect analog supply ground for sample clock phase locked loop analog supply voltage for sample clock phase locked loop (2.5 V) digital supply ground for sample clock phase locked loop digital supply voltage for sample clock phase locked loop (2.5 V) test reset input for boundary scan test (active LOW); note 2 test clock input for boundary scan test; note 2 test data input for boundary scan test; note 2 test mode select input for boundary scan test or scan test; note 2 test data output for boundary scan test
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
SYMBOL VSSA(EP) VDDA(EP) AGCANA Notes
PIN(1) 158 159 160
TYPE - - -
DESCRIPTION external analog pad supply ground external analog pad supply voltage (3.3 V) analog test pad (should be connected to analog ground for application)
1. For pin type description see Table 1. 2. For board design without boundary scan implementation connect pins TRST, TCK, TDI and TMS to ground. Table 1 Pin type description DESCRIPTION analog input digital input digital output digital input or output
TYPE A I O I/O
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
153 TRST 152 VDDD(PLL)(S)
151 VSSD(PLL)(S) 150 VDDA(PLL)(S)
144 VSSD(IC9) 143 VDDD(EP10)
142 VSSD(EP10) 141 HSYNC
146 VSS(PLL)(P) 145 VDDD(IC9)
133 CSG8 132 VDDD(EP9)
126 CSG3 125 VDDD(EP8)
131 VSSD(EP9)
124 VSSD(EP8) 123 VDDD(IC8)
handbook, full pagewidth
160 AGCANA 159 VDDA(EP) 158 VSSA(EP) 157 TDO
149 VSSA(PLL)(S) 148 n.c. 147 VDD(PLL)(P)
122 VSSD(IC8)
127 CSG4/A1
138 OUTEN
140 VSYNC
134 CSG9
130 CSG7
129 CSG6
128 CSG5
135 VCLK
139 PWM
137 INVB
136 INVA
156 TMS
154 TCK
VSSA(BIAS)(B) BIN VDDA(ADC)(B) REF_B VSSA(ADC)(B) VDDA(B) VSSA(B) VDDA(IB)
1 2 3 4 5 6 7 8
121 PF7 120 PF6 119 PF5 118 PF4 117 PF3 116 PF2 115 PF1 114 PF0 113 VDDD(EP7) 112 VSSD(EP7) 111 PE7 110 PE6 109 PE5 108 PE4 107 PE3 106 PE2 105 PE1 104 PE0 103 VDDD(IC7) 102 VSSD(IC7) 101 VDDD(EP6) 100 VSSD(EP6) 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VDDD(IC6) VSSD(IC6) VDDD(EP5) VSSD(EP5) PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 80
RBIAS 9 VSSA(BIAS)(SOG) 10 SOGIN VSSA(BIAS)(G) GIN VDDA(ADC)(G) REF_G VSSA(ADC)(G) VDDA(G) VSSA(G) VSSA(BIAS)(R) RIN VDDA(ADC)(R) REF_R VSSA(ADC)(R) VDDA(R) VSSA(R) VDDD(IC1) n.c. n.c. VSSD(IC1) n.c. n.c. VDDD(IC2) n.c. n.c. VSSD(IC2) n.c. RESERVED1 VDDD(IC3) VSSD(IC3) n.c. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 VDDD(EP4)
155 TDI
SAA6713AH
VDDD(EP3)
VDDD(EP1)
VDDD(EP2)
CSG2/A0 VSSD(EP2)
RESERVED3 VSSD(IC4)
RESERVED2
CLK VSSD(EP1)
PA7 VSSD(EP3)
PB7 VSSD(EP4)
VSSD(IC5) VDDD(IC5)
PB2
PB3
PB4
PB5
PB0
PA0
PA1
PA2
PA3
PA4
PA5
CSG0
VDDD(IC4)
CSG1
RST
PCLK
SDA
SCL
PA6
PB1
PB6
INT
MHC278
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7 FUNCTIONAL DESCRIPTION 7.1.2 I2C-BUS INTERFACE
SAA6713AH
In this chapter detailed information for the general configuration of the SAA6713AH is provided as well as detailed background information belonging to certain submodules of the device. Due to the high complexity of the device functionality this section should be studied very carefully. 7.1 7.1.1 Programming registers CONFIGURATION PARAMETER MAPPING
The I2C-bus serial interface consists of two pins: the serial clock pin SCL and the serial data pin SDA.
7.1.2.1
Transmission bit rate
The SAA6713AH operation is controlled by configuration parameters, that can be multiple-bit words or consist of only a single bit. The configuration parameters are mapped to bits of the 8 bit I2C-bus programming registers, that are accessible via the I2C-bus interface. Read-out data such as measurement results or interrupt states is mapped to readable I2C-bus registers. The I2C-bus registers are organized in pages. Generally, a register can only be accessed if the particular page is activated with the exception of global registers, so non-global registers are addressed by the I2C-bus subaddress in combination with the matching active page, but global registers are addressed by the subaddress independently of the active page. The global registers are mapped to I2C-bus subaddresses F8H to FFH. The active page is defined by page_select at subaddress FFH. In general, registers belonging to the same functional unit are mapped onto the same page. The I2C-bus register pages are shown in Table 2. Table 2 PAGE 0 1 2 3 4 5 6 7 8 9 10 11 I2C-bus register pages FUNCTIONAL UNIT control unit and clock generator ADC control mode detection auto-adjustment input interface and picture generator colour processing decoupling FIFO scalers OSD OSD colour definition gamma correction and dithering TFT output interface
The I2C-bus interface supports transmission speeds of up to 3.4 Mbits/s, given that a minimum system clock rate is provided. The required system clock rate depends on the target I2C-bus bit rate, which is the clock rate applied to pin SCL, and the spike suppression mode selected by iic_spike_mode in register IIC_MODE (03H at page 0) as shown in Table 3. If iic_spike_mode is set to 2, a high oversampling rate is used and the most effective spike suppression is provided. Table 3 I2C-bus spike suppression modes SYSTEM CLOCK >6 x I2C-bus bit rate >6 x I2C-bus bit rate >16 x I2C-bus bit rate not used DESCRIPTION 2-out-of-2 filter 2-out-of-3 majority filter 4-out-of-4 filter
iic_spike_ mode[1:0] 00 01 10 11
7.1.2.2
I2C-bus transmission timing
The SAA6713AH only operates as a slave and the clock pin SCL is exclusively input. Data is transmitted and received at I/O pin SDA. The SDA is an open-drain stage with an external pull-up resistor. When a logic 0 is applied, the bus is pulled to LOW-level by the output buffer. When a logic 1 is applied, the output buffer switches to 3-state and the pull-up resistor pulls the bus up to HIGH-level. Data transfers are initiated by an I2C-bus master device by sending the start condition, which is a change from HIGH-to-LOW level at SDA when SCL is at HIGH-level (see Fig.3). Data is transmitted byte wise. Data changes on SDA are allowed only when SCL is at LOW-level and data is sampled on the positive edge of SCL. The first transmitted byte is the recipients I2C-bus device address and the data transfer direction bit. All byte transfers are acknowledged by the recipient by pulling SDA to LOW-level for the following cycle.
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
If the write mode was selected, the bus master sends a byte containing the starting subaddress and then a series of data bytes. In case the read mode was selected, the addressed slave returns a series of data bytes. A read transfer is preceded by a write transfer that transmits the starting subaddress. Data transfers are aborted by the stop condition, when SDA is changed by the master from LOW-to-HIGH level when SCL is at HIGH-level (see Fig.4).
SAA6713AH
The four possible I2C-bus device addresses are selected via resistor strapping at pins CSG2/A0 and CSG4/A1 (see Table 5). During the hardware reset (pin RST = LOW), pins CSG2/A0 and CSG4/A1 are 3-stated. Their status at the trailing edge of signal RST will latch and determine the device address. Pull-up and pull-down resistors (4.7 k suggested) select the address. An internal pull-down resistance of approximately 100 k is provided and eliminates potentially the need for any external strapping resistor. After reset, the pins carry the output of the programmable signal generators. Table 5 Device address selection STRAPPING RESISTOR PIN CSG4/A1 pull-down pull-down pull-up pull-up PIN CSG2/A0 pull-down pull-up pull-down pull-up
7.1.2.3
I2C-bus device address
Bits A0 and A1 of the I2C-bus device address are externally selected by two input pins CSG2/A0 and CSG4/A1. The device address (byte) of the SAA6713AH is shown in Table 4. Table 4 MSB DEVICE ADDRESS BITS 0 1 1 1 0 A1 A0 I2C-bus device address byte
I2C-BUS DEVICE ADDRESS 70H LSB R/W 0/1 72H 74H 76H
handbook,SCL full pagewidth
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
R7
R6
R5
MHB248
START condition
acknowledge
Fig.3 Start of a data transfer.
handbook, full pagewidth SCL
SDA
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
A/A
acknowledge/ not acknowledge
STOP condition
MHB249
Fig.4 End of a data transfer.
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.1.2.4 I2C-bus subaddress 7.1.2.6 I2C-bus test register
SAA6713AH
When transmitting a series of data bytes, after a data byte has been written or read, the subaddress for the following byte is automatically updated to allow burst access. During burst access a sequence of data bytes is written or read without repeated device or subaddressing. In general, the I2C-bus auto-increment feature uses the next higher subaddress as the succeeding byte's subaddress. Auto-incrementing is suppressed for several addresses that provide access to the on-chip parameter RAM. In the event of upscaler register USC_LUT_DATA (02H at page 7) subsequent data is written to the same subaddress and the scaling curve RAM address is incremented instead. For OSD registers OSDT_PROP2 to OSDT_PROP0, OSDB_DEF and OSDP_DEF (0FH to 11H, 31H and 4CH at page 8) and colour look-up table register CL_VALUE_LO (03H at page 10) different subaddress update modes are selectable and are described in the respective subsection.
Register IIC_TEST (02H at page 0) is a read and write register that can be used to verify correct operations of the I2C-bus. Any programmed value can be read back. 7.1.3 I2C-BUS REGISTER LISTING
The global registers are listed in Table 6. The page-mapped registers are listed for each register page in Tables 7 to 17.
7.1.2.5
Multiple byte parameters
Parameters or read-out data words consisting of more than 8 bits are mapped into the address space in the order highest byte at the lowest address to lowest byte at the highest address. Multiple byte configuration parameters have to be written lowest address first and only become effective, once the byte of the highest address was written. Multiple byte read registers have to be read-out in the same order.
2004 Apr 05
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 6 Global configuration registers 2004 Apr 05 15 Philips Semiconductors
XGA analog input flat panel controller
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
Global control: FAH to FFH GC_MISC0 FAH W 00H avi_ reserved noclamp_ sog_en avi_ reserved noclamp_ pol reset_ csdec_n int_iif_en int_iif_clr int_iif_stat int_mode_ en int_mode int_mode reserved int_auto_ en int_auto int_auto reset_fclk int_fifo_en int_fifo int_fifo reset_bclk reset_oif
GC_MISC1
FBH W
FFH
GC_RESET GC_INT_MASK GC_INT_CLR GC_INT_STAT GC_PAGE Table 7
FCH W FDH W FEH W FEH R
1FH -0-0 0000 -1-1 1111 -0-0 0000
int_osd_en int_oif_en int_osd int_osd int_oif int_oif
FFH R/W ---- 0000
page_select[3:0]
General control configuration registers (page 0); note 1 ADR R/W RESET D7 D6 D5 D4 D3 D2 D1 D0
REGISTER
Device identification: 00H to 03H DEV_ID_HI DEV_ID_LO IIC_TEST IIC_MODE 00H R 01H R 03H W 13H 1CH ---- --00 --00 0000 ---- 1111 --11 0110 vclk_in_en cfgclk_ select cfgclk_on osd_ cfgclk_on aaclk_on dscclk_on dev_id[15:8] dev_id[7:0] iic_test[7:0] iic_spike_mode[1:0]
02H R/W 00H
Clock distribution: 10H to 12H CD_CLK_EN CD_CLK_AUTO CD_CLK_MUX 10H W 11H W 12H W uscclk_on uscclk_ auto osdclk_on osdclk_ auto
aaclk_auto dscclk_ auto fifo_fclk frontend_ bclk
SAA6713AH
Product specification
bclk_in_en clk_div4
Sync distribution: 18H and 19H SYNC_SEL 18H W ---0 0000 hs_regen_ vsync_out_ reserved in_en en sog_out_ en sog_en
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 16 Philips Semiconductors REGISTER SYNC_DIS ADR R/W 19H W RESET -000 0000 D7 D6 reserved D5 mdd_cs_ sog_en D4 mdd_hs_ regen_on D3 D2 reserved D1 D0
XGA analog input flat panel controller
iif_cs_sog_ iif_hs_ en regen_on
PLL programming: 20H to 29H CD_PLL_CTRL CD_PLL_P_HI CD_PLL_P_LO CD_PLL_HI CD_PLL_LO CD_LPLL_HI CD_LPLL_LO CD_LPLL_PHA CD_LPLL_PD CD_PLL_LOCK 20H W 21H W 22H W 23H W 24H W 25H W 26H W 27H W 28H W 29H R -010 -000 00H 00H --00 0000 00H --00 0000 00H ---0 0000 -100 0000 ---- -XXX phase_ auto phase_ select line_pll_n_div[7:0] line_pll_phase[4:0] pd_pll_phase[4:0] phase_ inlock pll_inlock llpll_inlock pll_n_div[7:0] line_pll_m_div[1:0] line_pll_n_div[11:8] line_pll_ hs_pol pll_pre_div[15:8] pll_pre_div[7:0] pll_m_div[1:0] pll_n_div[11:8] line_pll_ vs_pol line_pll_en pll_src pll_pre_ div_en pll_en
Interface timing: 34H and 35H IT_CTRL IT_PLL Note 1. X = don't care. Table 8 ADC configuration registers (page 1) ADR R/W RESET ---- -000 00H 00H 00H adc_red_brightness[7:0] adc_red_contrast[7:0] adc_green_brightness[7:0] D7 D6 D5 D4 D3 D2 D1 D0 34H W 35H W ---- --11 ---- 1111 pll_coast_ pol adc_pon_ pol bigger_ out_pol
pll_pon_pol llpll_coast_ llpll_pon_ pol pol
REGISTER
ADC programming: 00H to 06H ADC_CTRL ADC_R_BRI ADC_R_CON ADC_G_BRI 00H W 01H W 02H W 03H W sog_vs_ disable reserved sync_on_ green_en
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 17 Philips Semiconductors REGISTER ADC_G_CON ADC_B_BRI ADC_B_CON Table 9 ADR R/W 04H W 05H W 06H W RESET 00H 00H 00H D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
adc_green_contrast[7:0] adc_blue_brightness[7:0] adc_blue_contrast[7:0]
Mode detection configuration registers (page 2); note 1 ADR R/W RESET -000 0000 D7 D6 D5 D4 D3 D2 D1 D0
REGISTER
Mode detection: 00H to 0EH MD_CTRL MD_INT_EN MD_POL MD_V_LINE_HI MD_V_LINE_LO MD_H_CLK_HI MD_H_CLK_LO MD_V_CLK_HI MD_V_CLK_MD MD_V_CLK_LO MD_INT_HI MD_INT_LO MD_ACT_INT MD_SYNC_ACT MD_ACT_IEN Note 1. X = don't care. 00H W 01H W 02H R 03H R 04H R 05H R 06H R 07H R 08H R 09H R 0AH R 0BH R 0CH R 0DH R 0EH W no_vsync_ clear_int int_en v_clocks_ int_en int_lock h_clocks_ int_en jitter_ detected v_lines[7:0] h_clocks[15:8] h_clocks[7:0] v_clocks[23:16] v_clocks[15:8] v_clocks[7:0] vsync_int jitter_int vsync_pol_ hsync_pol_ no_vsync_ no_hsync_ int int int int v_lines_int h_clocks_ int reserved reserved reserved reserved reserved reserved reserved reserved asog_act_ int asog_ active asog_int_ en v_clocks_ int delay_ vsync h_clocks_ accu h_clocks_ cont md_on
0000 0000 jitter_int_en v_lines_ int_en ---0 0011 ---- -000 00H 00H 00H 00H 00H 00H --00 0000 ---- -000 X000 0000 reserved --00 0000 0000 0000 reserved
no_hsync_ vsync_int_ vsync_pol_ hsync_pol_ int_en en int_en int_en vsync_pol hsync_pol v_lines[10:8] no_vsync no_hsync
acsvs_act_ avs_act_int ahs_act_int int acsvs_ active avs_active ahs_active
SAA6713AH
Product specification
acsvs_int_ avs_int_en ahs_int_en en
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 10 Auto-adjustment configuration registers (page 3); note 1 2004 Apr 05 18 Philips Semiconductors
XGA analog input flat panel controller
REGISTER
ADR R/W
RESET ---- -XXX XX ---- XXXX XX ---- -XXX XX ---- XXXX XX XX XX XX XX XX XX --01 1000 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
D7
D6
D5
D4
D3
D2
D1
D0
Auto-adjustment: 08H to 16H and 40H to 4DH AA_RC0_HI AA_RC0_LO AA_RR0_HI AA_RR0_LO AA_RC1_HI AA_RC1_LO AA_RR1_HI AA_RR1_LO AA_RCR0 AA_RCG0 AA_RCB0 AA_RCR1 AA_RCG1 AA_RCB1 AA_CTRL AA_EPR0 AA_EPG0 AA_EPB0 AA_EPR1 AA_EPG1 AA_EPB1 AA_ER0_HI AA_ER0_LO AA_EC0_HI AA_EC0_LO AA_ER1_HI AA_ER1_LO AA_EC1_HI AA_EC1_LO 08H W 09H W 0AH W 0BH W 0CH W 0DH W 0EH W 0FH W 10H W 11H W 12H W 13H W 14H W 15H W 16H W 40H R 42H R 44H R 41H R 43H R 45H R 46H R 47H R 48H R 49H R 4AH R 4BH R 4CH R 4DH R ref_col_0[10:8] ref_col_0[7:0] ref_row_0[11:8] ref_row_0[7:0] ref_col_1[10:8] ref_col_1[7:0] ref_row_1[11:8] ref_row_1[7:0] ref_colour_0[23:16] ref_colour_0[15:8] ref_colour_0[7:0] ref_colour_1[23:16] ref_colour_1[15:8] ref_colour_1[7:0] aa_cycles[1:0] ref_pixel_red_0[7:0] ref_pixel_green_0[7:0] ref_pixel_blue_0[7:0] ref_pixel_red_1[7:0] ref_pixel_green_1[7:0] ref_pixel_blue_1[7:0] eval_row_0[15:8] eval_row_0[7:0] eval_col_0[15:8] aa_submode[1:0] aa_mode[1:0]
SAA6713AH
eval_col_0[7:0] eval_row_1[15:8] eval_row_1[7:0] eval_col_1[15:8] eval_col_1[7:0]
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Note 2004 Apr 05 19 Philips Semiconductors
XGA analog input flat panel controller
1. X = don't care. Table 11 Input interface configuration registers (page 4) REGISTER ADR R/W RESET D7 D6 D5 D4 D3 D2 D1 D0
Input interface: 00H to 0FH II_CTRL II_SYNC_CTRL II_ADC_CTRL II_CLAMP_ON II_CLAMP_OFF II_GAINC_ON II_GAINC_OFF II_HLEN_HI II_HLEN_LO II_VLEN_HI II_VLEN_LO II_HOFF_HI II_HOFF_LO II_VOFF_HI II_VOFF_LO II_HJIT 00H W 01H W 02H W 03H W 04H W 05H W 06H W 07H W 08H W 09H W 0AH W 0BH W 0CH W 0DH W 0EH W 0FH W 0-00 0101 test_out_ en 110- -011 sync_clk_ edge 1001 1111 delay_vs 02H 05H 01H 01H ---- 0000 3CH ---- 0000 28H ---- 0000 00H ---- 0000 00H 05H in_v_offset[7:0] hs_jitter_th[7:0] in_h_offset[7:0] in_v_offset[11:8] in_v_length[7:0] in_h_offset[11:8] in_h_length[7:0] in_v_length[11:8] ext_clk_ edge reverse_ field_id reserved gainc_en interlace_ on test_pic_on ext_select hsync_ edge clamp_en set to `0' vs_pol gainc_pol in_form_on hs_pol clamp_pol
convert_2s reserved
clamp_on_delay[7:0] clamp_off_delay[7:0] gainc_on_delay[7:0] gainc_off_delay[7:0] in_h_length[11:8]
Picture generator: 10H to 1CH PG_CTRL PG_HTOTAL_HI PG_HTOTAL_LO PG_VTOTAL_HI PG_VTOTAL_LO PG_HSTEP1 PG_HINC1 PG_HSTEP2 10H W 11H W 12H W 13H W 14H W 15H W 16H W 17H W 0010 0010 invert ---- 0000 51H ---- 0000 35H 01H 02H 00H v_length_total[7:0] h_step1[7:0] h_colour_inc1[7:0] h_step2[7:0] h_length_total[7:0] v_length_total[11:8] white_ border h_ramp_r h_ramp_g h_ramp_b v_ramp_r v_ramp_g v_ramp_b
h_length_total[11:8]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 20 Philips Semiconductors REGISTER PG_HINC2 PG_VSTEP1 PG_VINC1 PG_VSTEP2 PG_VINC2 ADR R/W 18H W 19H W 1AH W 1BH W 1CH W RESET FFH 14H FFH 01H FFH D7 v_step1[7:0] v_colour_inc1[7:0] v_step2[7:0] v_colour_inc2[7:0] D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
h_colour_inc2[7:0]
Table 12 Colour processing configuration registers (page 5) REGISTER ADR R/W RESET D7 D6 D5 D4 D3 D2 D1 D0
Colour processing: 00H to 0BH CP_GAIN_Y CP_GAIN_CB CP_GAIN_CR CP_OFFS_Y CP_OFFS_CB CP_OFFS_CR CP_GAIN_R CP_GAIN_G CP_GAIN_B CP_OFFS_R CP_OFFS_G CP_OFFS_B 00H W 01H W 02H W 03H W 04H W 05H W 06H W 07H W 08H W 09H W 0AH W 0BH W 80H 80H 80H 00H 00H 00H 80H 80H 80H 00H 00H 00H gain_y[7:0] gain_cb[7:0] gain_cr[7:0] offset_y[7:0] offset_cb[7:0] offset_cr[7:0] gain_r[7:0] gain_g[7:0] gain_b[7:0] offset_r[7:0] offset_g[7:0] offset_b[7:0]
Table 13 Decoupling FIFO configuration registers (page 6) REGISTER ADR R/W RESET D7 D6 D5 D4 D3 D2 D1 D0
Decoupling FIFO: 00H and 01H DF_THLD DF_CTRL 00H W 01H W 01H ---- --10 fifo_threshold[7:0]
SAA6713AH
Product specification
line_lock
reserved
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 14 Scaler configuration registers (page 7); note 1 2004 Apr 05 21 Philips Semiconductors
XGA analog input flat panel controller
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
Upscaler: 00H to 09H, 0DH, 0FH, 11H and 14H to 18H USC_CTRL USC_LUT_ADR USC_LUT_DATA USC_H_INC_HI USC_H_INC_LO USC_H_CORR USC_V_INC_HI USC_V_INC_LO USC_V_CORR USC_H_PHA USC_V_PHA_0 USC_V_PHA_1 USC_PHA_SEL Reserved 00H W 01H W 02H W 03H W 04H W 05H W 06H W 07H W 08H W 09H W 0DH W 0FH W 11H W 14H - to 18H 1010 1101 filter_type[1:0] 1100 0000 v_lut_sel XX ---- 0000 55H -010 0010 ---- 0000 0110 0000 v_scale_incr[7:0] -000 0000 --00 0000 --00 0000 --00 0000 ---- -000 - v_scale_corr[6:0] h_phase_off[5:0] v_phase_off_0[5:0] v_phase_off_1[5:0] v_phase_off_sel[1:0] set to `0' h_scale_incr[7:0] h_scale_corr[6:0] v_scale_incr[11:8] lut_data[7:0] h_scale_incr[11:8] h_lut_sel 1 lut_addr[5:0] 0 0 0 usc_flip_h usc_en
Downscaler: 40H to 44H DS_EN DS_HSC DS_HSC_CO DS_VSC DS_VSC_CO Note 1. X = don't care. 40H W 41H W 42H W 43H W 44H W ---- --10 -011 0011 -001 0100 -011 0000 -000 0000 dsc_h_incr[6:0] dsc_h_incr_corr[6:0] dsc_v_incr[6:0] dsc_v_incr_corr[6:0] flip_h dsc_en
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 15 Definition of OSD configuration registers (pages 8 and 9); note 1 2004 Apr 05 22 Philips Semiconductors
XGA analog input flat panel controller
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
Control registers (page 8) OSD TEXT: 00H TO 1FH OSDT_CTRL0 OSDT_CTRL1 00H W 01H W X000 0000 areafill_ start ---- 0011 window_ shadow h_flip v_flip rotate_right zoom[1:0] txt_ shadow_ style bg_alpha[7:0] fg_alpha[7:0] text_column[7:0] text_row[7:0] x_position[10:8] x_position[7:0] y_position[10:8] y_position[7:0] window_shadow_height[2:0] blink_delay[7:0] cursor_column[7:0] cursor_row[7:0] blink_mask shadow_ bg_mask mask blink[1:0] bg_colour[2:0] charcode[7:0] font_horizontal_resolution[4:0] fg_mask shadow code_mask write_mode[2:0] bg_trans fg_trans bg_alpha ROM fg_alpha charcode [8] window_shadow_width[2:0] 0 1 text_on 1
OSDT_BGA OSDT_FGA OSDT_WX OSDT_WY OSDT_PX_HI OSDT_PX_LO OSDT_PY_HI OSDT_PY_LO OSDT_WSHAD OSDT_BDLY OSDT_CURX OSDT_CURY OSDT_MASK OSDT_PROP2 OSDT_PROP1 OSDT_PROP0 OSDT_FR_X OSDT_FR_Y OSDT_SC_HI
02H W 03H W 04H W 05H W 06H W 07H W 08H W 09H W 0AH W 0BH W
7FH 7FH 28H 1EH ---- -000 00H ---- -000 00H -000 -000 3CH
0CH R/W 00H 0DH R/W 00H 0EH W 0FH W 10H W 11H W 12H W 13H W 14H W 1111 1111 -000 0000 0001 1110 00H ---0 1100 ---1 0010 ---- ---0
fg_colour[2:0]/palette[2:0]
SAA6713AH
Product specification
font_vertical_resolution[4:0] sc_ startcode [8] sc_startcode[7:0]
OSDT_SC_LO
15H W
00H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 23 Philips Semiconductors REGISTER OSDT_CC_HI ADR R/W 16H W RESET 0--- ---0 D7 single_ char_def define_charcode[7:0] definition_mask[7:0] char_definition[7:0] fill_area_upper_left_corner_x[7:0] fill_area_upper_left_corner_y[7:0] fill_area_bottom_right_corner_x[7:0] fill_area_bottom_right_corner_y[7:0] slider_border[3:0] slider_offset[3:0] slider_style slider_gap[3:0] D6 D5 D4 D3 D2 D1 D0 define_ charcode [8]
XGA analog input flat panel controller
OSDT_CC_LO OSDT_CMASK OSDT_CDEF OSDT_FAULX OSDT_FAULY OSDT_FABRX OSDT_FABRY OSDT_SLP1 OSDT_SLP0
17H W 18H W 19H W 1AH W 1BH W 1CH W 1DH W 1EH W 1FH W
00H FFH 00H XX XX XX XX 0001 0001 ---0 0001 -000 0000 -XX0 0011 7FH 7FH ---- -100 00H ---- -000 04H ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H XX XX
OSD BITMAP: 20H TO 31H OSDB_CTRL0 OSDB_CTRL1 OSDB_BGA OSDB_FGA OSDB_SX_HI OSDB_SX_LO OSDB_SY_HI OSDB_SY_LO OSDB_PX_HI OSDB_PX_LO OSDB_PY_HI OSDB_PY_LO OSDB_CX_HI OSDB_CX_LO OSDB_CY_HI OSDB_CY_LO OSDB_MASK OSDB_DEF 20H W 21H W 22H W 23H W 24H W 25H W 26H W 27H W 28H W 29H W 2AH W 2BH W 2CH W 2DH W 2EH W 2FH W 30H W 31H W bitmap_ behind bpp[1:0] bg_alpha[7:0] fg_alpha[7:0] width[10:8] width[7:0] height[10:8] height[7:0] x_position[10:8] x_position[7:0] y_position[10:8] y_position[7:0] cursor_column[10:8] cursor_column[7:0] cursor_row[10:8] cursor_row[7:0] definition_mask[7:0] pixel_definition[7:0] h_flip v_flip bg_trans rotate_right zoom[1:0] fg_trans 0 1 bitmap_on 1
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 24 Philips Semiconductors REGISTER ADR R/W RESET D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
OSD POINTER: 40H TO 4CH OSDP_CTRL0 OSDP_CTRL1 OSDP_BGA OSDP_FGA OSDP_AD OSDP_DW OSDP_PX_HI OSDP_PX_LO OSDP_PY_HI OSDP_PY_LO OSDP_CX OSDP_CY OSDP_DEF 40H W 41H W 42H W 43H W 44H W 45H W 46H W 47H W 48H W 49H W 4AH W 4BH W 4CH W 0000 0000 --00 0011 FFH FFH 1EH ---- --00 ---- -000 00H ---- -000 00H ---0 0000 ---0 0000 00H pixel_definition[7:0] y_position[7:0] cursor_column[4:0] cursor_row[4:0] x_position[7:0] y_position[10:8] bg_alpha[7:0] fg_alpha[7:0] anim_delay[7:0] defwidth[1:0] x_position[10:8] autosel_en buffer_sel h_flip anim_int_ en v_flip bg_trans rotate_right zoom[1:0] fg_trans 0 1 pointer_on 1
Colour definitions (page 9) OSD TEXT COLOURS: 00H TO 92H OSDT_FGC0R OSDT_FGC0G OSDT_FGC0B OSDT_FGC1R OSDT_FGC1G OSDT_FGC1B OSDT_FGC2R OSDT_FGC2G OSDT_FGC2B OSDT_FGC3R OSDT_FGC3G OSDT_FGC3B OSDT_FGC4R OSDT_FGC4G 00H W 01H W 02H W 03H W 04H W 05H W 06H W 07H W 08H W 09H W 0AH W 0BH W 0CH W 0DH W 00H 00H 00H FFH 00H 00H 00H FFH 00H 00H 00H FFH FFH FFH osd_text_foreground_colour0_red[7:0] osd_text_foreground_colour0_green[7:0] osd_text_foreground_colour0_blue[7:0] osd_text_foreground_colour1_red[7:0] osd_text_foreground_colour1_green[7:0] osd_text_foreground_colour1_blue[7:0] osd_text_foreground_colour2_red[7:0] osd_text_foreground_colour2_green[7:0] osd_text_foreground_colour2_blue[7:0] osd_text_foreground_colour3_red[7:0] osd_text_foreground_colour3_green[7:0] osd_text_foreground_colour3_blue[7:0] osd_text_foreground_colour4_red[7:0] osd_text_foreground_colour4_green[7:0]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 25 Philips Semiconductors REGISTER OSDT_FGC4B OSDT_FGC5R OSDT_FGC5G OSDT_FGC5B OSDT_FGC6R OSDT_FGC6G OSDT_FGC6B OSDT_FGC7R OSDT_FGC7G OSDT_FGC7B OSDT_BGC0R OSDT_BGC0G OSDT_BGC0B OSDT_BGC1R OSDT_BGC1G OSDT_BGC1B OSDT_BGC2R OSDT_BGC2G OSDT_BGC2B OSDT_BGC3R OSDT_BGC3G OSDT_BGC3B OSDT_BGC4R OSDT_BGC4G OSDT_BGC4B OSDT_BGC5R OSDT_BGC5G OSDT_BGC5B OSDT_BGC6R OSDT_BGC6G OSDT_BGC6B OSDT_BGC7R ADR R/W 0EH W 0FH W 10H W 11H W 12H W 13H W 14H W 15H W 16H W 17H W 18H W 19H W 1AH W 1BH W 1CH W 1DH W 1EH W 1FH W 20H W 21H W 22H W 23H W 24H W 25H W 26H W 27H W 28H W 29H W 2AH W 2BH W 2CH W 2DH W RESET 00H 00H FFH FFH FFH 00H FFH FFH FFH FFH 00H 00H 00H FFH 00H 00H 00H FFH 00H 00H 00H FFH FFH FFH 00H 00H FFH FFH FFH 00H FFH FFH D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
osd_text_foreground_colour4_blue[7:0] osd_text_foreground_colour5_red[7:0] osd_text_foreground_colour5_green[7:0] osd_text_foreground_colour5_blue[7:0] osd_text_foreground_colour6_red[7:0] osd_text_foreground_colour6_green[7:0] osd_text_foreground_colour6_blue[7:0] osd_text_foreground_colour7_red[7:0] osd_text_foreground_colour7_green[7:0] osd_text_foreground_colour7_blue[7:0] osd_text_background_colour0_red[7:0] osd_text_background_colour0_green[7:0] osd_text_background_colour0_blue[7:0] osd_text_background_colour1_red[7:0] osd_text_background_colour1_green[7:0] osd_text_background_colour1_blue[7:0] osd_text_background_colour2_red[7:0] osd_text_background_colour2_green[7:0] osd_text_background_colour2_blue[7:0] osd_text_background_colour3_red[7:0] osd_text_background_colour3_green[7:0] osd_text_background_colour3_blue[7:0] osd_text_background_colour4_red[7:0] osd_text_background_colour4_green[7:0] osd_text_background_colour4_blue[7:0] osd_text_background_colour5_red[7:0] osd_text_background_colour5_green[7:0] osd_text_background_colour5_blue[7:0] osd_text_background_colour6_red[7:0] osd_text_background_colour6_green[7:0] osd_text_background_colour6_blue[7:0] osd_text_background_colour7_red[7:0]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 26 Philips Semiconductors REGISTER OSDT_BGC7G OSDT_BGC7B OSDT_P0C0R OSDT_P0C0G OSDT_P0C0B OSDT_P0C1R OSDT_P0C1G OSDT_P0C1B OSDT_P0C2R OSDT_P0C2G OSDT_P0C2B OSDT_P0C3R OSDT_P0C3G OSDT_P0C3B OSDT_P1C0R OSDT_P1C0G OSDT_P1C0B OSDT_P1C1R OSDT_P1C1G OSDT_P1C1B OSDT_P1C2R OSDT_P1C2G OSDT_P1C2B OSDT_P1C3R OSDT_P1C3G OSDT_P1C3B OSDT_P2C0R OSDT_P2C0G OSDT_P2C0B OSDT_P2C1R OSDT_P2C1G OSDT_P2C1B ADR R/W 2EH W 2FH W 30H W 31H W 32H W 33H W 34H W 35H W 36H W 37H W 38H W 39H W 3AH W 3BH W 3CH W 3DH W 3EH W 3FH W 40H W 41H W 42H W 43H W 44H W 45H W 46H W 47H W 48H W 49H W 4AH W 4BH W 4CH W 4DH W RESET FFH FFH 00H 00H 00H FFH 00H 00H 00H FFH 00H 00H 00H FFH FFH FFH 00H 00H FFH FFH FFH 00H FFH FFH FFH FFH 40H 40H 40H 80H 00H 00H D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
osd_text_background_colour7_green[7:0] osd_text_background_colour7_blue_7[7:0] osd_palette0_colour0_red[7:0] osd_palette0_colour0_green[7:0] osd_palette0_colour0_blue[7:0] osd_palette0_colour1_red[7:0] osd_palette0_colour1_green[7:0] osd_palette0_colour1_blue[7:0] osd_palette0_colour2_red[7:0] osd_palette0_colour2_green[7:0] osd_palette0_colour2_blue[7:0] osd_palette0_colour3_red[7:0] osd_palette0_colour3_green[7:0] osd_palette0_colour3_blue[7:0] osd_palette1_colour0_red[7:0] osd_palette1_colour0_green[7:0] osd_palette1_colour0_blue[7:0] osd_palette1_colour1_red[7:0] osd_palette1_colour1_green[7:0] osd_palette1_colour1_blue[7:0] osd_palette1_colour2_red[7:0] osd_palette1_colour2_green[7:0] osd_palette1_colour2_blue[7:0] osd_palette1_colour3_red[7:0] osd_palette1_colour3_green[7:0] osd_palette1_colour3_blue[7:0] osd_palette2_colour0_red[7:0] osd_palette2_colour0_green[7:0] osd_palette2_colour0_blue[7:0] osd_palette2_colour1_red[7:0] osd_palette2_colour1_green[7:0] osd_palette2_colour1_blue[7:0]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 27 Philips Semiconductors REGISTER OSDT_P2C2R OSDT_P2C2G OSDT_P2C2B OSDT_P2C3R OSDT_P2C3G OSDT_P2C3B OSDT_P3C0R OSDT_P3C0G OSDT_P3C0B OSDT_P3C1R OSDT_P3C1G OSDT_P3C1B OSDT_P3C2R OSDT_P3C2G OSDT_P3C2B OSDT_P3C3R OSDT_P3C3G OSDT_P3C3B OSDT_P4C0R OSDT_P4C0G OSDT_P4C0B OSDT_P4C1R OSDT_P4C1G OSDT_P4C1B OSDT_P4C2R OSDT_P4C2G OSDT_P4C2B OSDT_P4C3R OSDT_P4C3G OSDT_P4C3B OSDT_P5C0R OSDT_P5C0G ADR R/W 4EH W 4FH W 50H W 51H W 52H W 53H W 54H W 55H W 56H W 57H W 58H W 59H W 5AH W 5BH W 5CH W 5DH W 5EH W 5FH W 60H W 61H W 62H W 63H W 64H W 65H W 66H W 67H W 68H W 69H W 6AH W 6BH W 6CH W 6DH W RESET 00H 80H 00H 00H 00H 80H 80H 80H 00H 00H 80H 80H 80H 00H 80H 80H 80H 80H 00H 00H 00H 3FH 3FH 3FH 7FH 7FH 7FH FFH FFH FFH 00H 00H D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
osd_palette2_colour2_red[7:0] osd_palette2_colour2_green[7:0] osd_palette2_colour2_blue[7:0] osd_palette2_colour3_red[7:0] osd_palette2_colour3_green[7:0] osd_palette2_colour3_blue[7:0] osd_palette3_colour0_red[7:0] osd_palette3_colour0_green[7:0] osd_palette3_colour0_blue[7:0] osd_palette3_colour1_red[7:0] osd_palette3_colour1_green[7:0] osd_palette3_colour1_blue[7:0] osd_palette3_colour2_red[7:0] osd_palette3_colour2_green[7:0] osd_palette3_colour2_blue[7:0] osd_palette3_colour3_red[7:0] osd_palette3_colour3_green[7:0] osd_palette3_colour3_blue[7:0] osd_palette4_colour0_red[7:0] osd_palette4_colour0_green[7:0] osd_palette4_colour0_blue[7:0] osd_palette4_colour1_red[7:0] osd_palette4_colour1_green[7:0] osd_palette4_colour1_blue[7:0] osd_palette4_colour2_red[7:0] osd_palette4_colour2_green[7:0] osd_palette4_colour2_blue[7:0] osd_palette4_colour3_red[7:0] osd_palette4_colour3_green[7:0] osd_palette4_colour3_blue[7:0] osd_palette5_colour0_red[7:0] osd_palette5_colour0_green[7:0]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 28 Philips Semiconductors REGISTER OSDT_P5C0B OSDT_P5C1R OSDT_P5C1G OSDT_P5C1B OSDT_P5C2R OSDT_P5C2G OSDT_P5C2B OSDT_P5C3R OSDT_P5C3G OSDT_P5C3B OSDT_P6C0R OSDT_P6C0G OSDT_P6C0B OSDT_P6C1R OSDT_P6C1G OSDT_P6C1B OSDT_P6C2R OSDT_P6C2G OSDT_P6C2B OSDT_P6C3R OSDT_P6C3G OSDT_P6C3B OSDT_P7C0R OSDT_P7C0G OSDT_P7C0B OSDT_P7C1R OSDT_P7C1G OSDT_P7C1B OSDT_P7C2R OSDT_P7C2G OSDT_P7C2B OSDT_P7C3R ADR R/W 6EH W 6FH W 70H W 71H W 72H W 73H W 74H W 75H W 76H W 77H W 78H W 79H W 7AH W 7BH W 7CH W 7DH W 7EH W 7FH W 80H W 81H W 82H W 83H W 84H W 85H W 86H W 87H W 88H W 89H W 8AH W 8BH W 8CH W 8DH W RESET 00H 7FH 00H 00H 00H 7FH 00H 00H 00H 7FH C0H C0H C0H 80H 80H 80H E0H E0H E0H 00H 00H 00H C0H C0H C0H E0H E0H E0H 80H 80H 80H 00H D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
osd_palette5_colour0_blue[7:0] osd_palette5_colour1_red[7:0] osd_palette5_colour1_green[7:0] osd_palette5_colour1_blue[7:0] osd_palette5_colour2_red[7:0] osd_palette5_colour2_green[7:0] osd_palette5_colour2_blue[7:0] osd_palette5_colour3_red[7:0] osd_palette5_colour3_green[7:0] osd_palette5_colour3_blue[7:0] osd_palette6_colour0_red[7:0] osd_palette6_colour0_green[7:0] osd_palette6_colour0_blue[7:0] osd_palette6_colour1_red[7:0] osd_palette6_colour1_green[7:0] osd_palette6_colour1_blue[7:0] osd_palette6_colour2_red[7:0] osd_palette6_colour2_green[7:0] osd_palette6_colour2_blue[7:0] osd_palette6_colour3_red[7:0] osd_palette6_colour3_green[7:0] osd_palette6_colour3_blue[7:0] osd_palette7_colour0_red[7:0] osd_palette7_colour0_green[7:0] osd_palette7_colour0_blue[7:0] osd_palette7_colour1_red[7:0] osd_palette7_colour1_green[7:0] osd_palette7_colour1_blue[7:0] osd_palette7_colour2_red[7:0] osd_palette7_colour2_green[7:0] osd_palette7_colour2_blue[7:0] osd_palette7_colour3_red[7:0]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 29 Philips Semiconductors REGISTER OSDT_P7C3G OSDT_P7C3B OSDT_SCR OSDT_SCG OSDT_SCB ADR R/W 8EH W 8FH W 90H W 91H W 92H W RESET 00H 00H 00H 00H 00H D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
osd_palette7_colour3_green[7:0] osd_palette7_colour3_blue[7:0] osd_shadow_colour_red[7:0] osd_shadow_colour_green[7:0] osd_shadow_colour_blue[7:0]
OSD BITMAP COLOURS: 93H TO C2 OSDB_C0R OSDB_C0G OSDB_C0B OSDB_C1R OSDB_C1G OSDB_C1B OSDB_C2R OSDB_C2G OSDB_C2B OSDB_C3R OSDB_C3G OSDB_C3B OSDB_C4R OSDB_C4G OSDB_C4B OSDB_C5R OSDB_C5G OSDB_C5B OSDB_C6R OSDB_C6G OSDB_C6B OSDB_C7R OSDB_C7G OSDB_C7B OSDB_C8R OSDB_C8G 93H W 94H W 95H W 96H W 97H W 98H W 99H W 9AH W 9BH W 9CH W 9DH W 9EH W 9FH W A0H W A1H W A2H W A3H W A4H W A5H W A6H W A7H W A8H W A9H W AAH W ABH W ACH W 00H 00H 00H FFH 00H 00H 00H FFH 00H 00H 00H FFH FFH FFH 00H 00H FFH FFH FFH 00H FFH FFH FFH FFH 40H 40H osd_bitmap_colour0_red[7:0] osd_bitmap_colour0_green[7:0] osd_bitmap_colour0_blue[7:0] osd_bitmap_colour1_red[7:0] osd_bitmap_colour1_green[7:0] osd_bitmap_colour1_blue[7:0] osd_bitmap_colour2_red[7:0] osd_bitmap_colour2_green[7:0] osd_bitmap_colour2_blue[7:0] osd_bitmap_colour3_red[7:0] osd_bitmap_colour3_green[7:0] osd_bitmap_colour3_blue[7:0] osd_bitmap_colour4_red[7:0] osd_bitmap_colour4_green[7:0] osd_bitmap_colour4_blue[7:0] osd_bitmap_colour5_red[7:0] osd_bitmap_colour5_green[7:0] osd_bitmap_colour5_blue[7:0] osd_bitmap_colour6_red[7:0] osd_bitmap_colour6_green[7:0]
SAA6713AH
osd_bitmap_colour6_blue[7:0] osd_bitmap_colour7_red[7:0] osd_bitmap_colour7_green[7:0] osd_bitmap_colour7_blue[7:0] osd_bitmap_colour8_red[7:0] osd_bitmap_colour8_green[7:0]
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 30 Philips Semiconductors REGISTER OSDB_C8B OSDB_C9R OSDB_C9G OSDB_C9B OSDB_C10R OSDB_C10G OSDB_C10B OSDB_C11R OSDB_C11G OSDB_C11B OSDB_C12R OSDB_C12G OSDB_C12B OSDB_C13R OSDB_C13G OSDB_C13B OSDB_C14R OSDB_C14G OSDB_C14B OSDB_C15R OSDB_C15G OSDB_C15B ADR R/W ADH W AEH W AFH W B0H W B1H W B2H W B3H W B4H W B5H W B6H W B7H W B8H W B9H W BAH W BBH W BCH W BDH W BEH W BFH W C0H W C1H W C2H W RESET 40H 80H 00H 00H 00H 80H 00H 00H 00H 80H 80H 80H 00H 00H 80H 80H 80H 00H 80H 80H 80H 80H D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
osd_bitmap_colour8_blue[7:0] osd_bitmap_colour9_red[7:0] osd_bitmap_colour9_green[7:0] osd_bitmap_colour9_blue[7:0] osd_bitmap_colour10_red[7:0] osd_bitmap_colour10_green[7:0] osd_bitmap_colour10_blue[7:0] osd_bitmap_colour11_red[7:0] osd_bitmap_colour11_green[7:0] osd_bitmap_colour11_blue[7:0] osd_bitmap_colour12_red[7:0] osd_bitmap_colour12_green[7:0] osd_bitmap_colour12_blue[7:0] osd_bitmap_colour13_red[7:0] osd_bitmap_colour13_green[7:0] osd_bitmap_colour13_blue[7:0] osd_bitmap_colour14_red[7:0] osd_bitmap_colour14_green[7:0] osd_bitmap_colour14_blue[7:0] osd_bitmap_colour15_red[7:0] osd_bitmap_colour15_green[7:0] osd_bitmap_colour15_blue[7:0]
OSD POINTER COLOURS: C3H TO CEH OSDP_C0R OSDP_C0G OSDP_C0B OSDP_C1R OSDP_C1G OSDP_C1B OSDP_C2R OSDP_C2G OSDP_C2B C3H W C4H W C5H W C6H W C7H W C8H W C9H W CAH W CBH W 00H 00H 00H FFH 00H 00H 00H FFH 00H osd_pointer_colour0_red[7:0] osd_pointer_colour0_green[7:0] osd_pointer_colour0_blue[7:0]
SAA6713AH
osd_pointer_colour1_red[7:0] osd_pointer_colour1_green[7:0] osd_pointer_colour1_blue[7:0] osd_pointer_colour2_red[7:0] osd_pointer_colour2_green[7:0] osd_pointer_colour2_blue[7:0]
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 31 Philips Semiconductors REGISTER OSDP_C3R OSDP_C3G OSDP_C3B Note 1. X = don't care. Table 16 Colour look-up table and dithering configuration registers (page 10) REGISTER ADR R/W RESET --00 0000 00H ---- --00 00H colour_value[7:0] colour_index[7:0] colour_value[9:8] D7 D6 D5 D4 D3 D2 D1 D0 ADR R/W CCH W CDH W CEH W RESET 00H 00H FFH D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
osd_pointer_colour3_red[7:0] osd_pointer_colour3_green[7:0] osd_pointer_colour3_blue[7:0]
Colour look-up table: 00H to 03H CL_CTRL CL_INDEX CL_VALUE_HI CL_VALUE_LO 00H W 01H W 02H W 03H W write_ hsynced quick_prog red_prog green_prog blue_prog cc_on
Temporal dithering: 80H to 83H DT_CTRL DT_COLMAP DT_MODE DT_NOISE 80H W 81H W 82H W 83H W 1--- 1--- 11-- ---- 00-- -100 0--- --0- dither_ bypass dither_colmap[1:0] dither_ dither_ rand_mode rand_mono dither_ add_noise dither_idx_ofs_reg[2:0] dither_ noise_mag dither_out_ bits
Table 17 Output interface configuration registers (page 11); note 1 REGISTER ADR R/W RESET D7 D6 D5 D4 D3 D2 D1 D0
Output interface: 01H to 39H, 40H to 4AH, 51H to 59H, 61H to 6AH, 71H to 7AH, 81H to 8AH, 91H to 9AH, A1H to AAH, B1H to BAH, C1H to CAH, D1H to DEH, E1H to EEH and F0H to F7H OI_WX_HI OI_WX_LO OI_INVA_DEL OI_INVB_DEL OI_PSX_HI 01H W 02H W 03H W 04H W 05H W ---- -000 02H 0000 0000 0000 0000 ---- -000 wait_column[7:0] pin_drv_inva[2:0] pin_drv_invb[2:0] inversion_A_pin_delay[4:0] inversion_B_pin_delay[4:0] picture_start_x[10:8] wait_column[10:8]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 32 Philips Semiconductors REGISTER OI_PSX_LO OI_PSY_HI OI_PSY_LO OI_ASX_HI OI_ASX_LO OI_ASY_HI OI_ASY_LO OI_PEX_HI OI_PEX_LO OI_PEY_HI OI_PEY_LO OI_AEX_HI OI_AEX_LO OI_AEY_HI OI_AEY_LO OI_FY_HI OI_FY_LO OI_FX_HI OI_FX_LO OI_ALX_HI OI_ALX_LO OI_PX_HI OI_PX_LO OI_WM OI_B0R OI_B0G OI_B0B OI_B1R OI_B1G OI_B1B OI_PAD OI_PBD ADR R/W 06H W 07H W 08H W 09H W 0AH W 0BH W 0CH W 0DH W 0EH W 0FH W 10H W 11H W 12H W 13H W 14H W 15H W 16H W 17H W 18H W 19H W 1AH W 1BH W 1CH W 1DH W 1EH W 1FH W 20H W 21H W 22H W 23H W 24H W 25H W RESET 09H ---- -000 07H ---- -000 07H ---- -000 05H ---- -000 54H ---- -000 3EH ---- -000 56H ---- -000 40H ---- -000 46H ---- -000 5EH ---- -000 5CH ---- -000 5AH ---- --01 --00 0011 --00 0001 --00 0000 --00 0111 --00 0101 --00 0100 0000 0000 0000 0000 pin_drv_pa[2:0] pin_drv_pb[2:0] MSB_align swap MSB_align swap MSB_align swap MSB_align swap MSB_align swap MSB_align swap inv inv inv inv inv inv picture_line_length[7:0] wait_mode[1:0] port_A_conf[2:0] port_B_conf[2:0] port_C_conf[2:0] port_D_conf[2:0] port_E_conf[2:0] port_F_conf[2:0] active_line_length[7:0] picture_line_length[10:8] blank_line_length[7:0] active_line_length[10:8] last_line[7:0] blank_line_length[10:8] active_end_y[7:0] last_line[10:8] active_end_x[7:0] active_end_y[10:8] picture_end_y[7:0] active_end_x[10:8] picture_end_x[7:0] picture_end_y[10:8] active_start_y[7:0] picture_end_x[10:8] active_start_x[7:0] active_start_y[10:8] picture_start_y[7:0] active_start_x[10:8] D7 D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
picture_start_x[7:0] picture_start_y[10:8]
SAA6713AH
Product specification
pin_delay[4:0] pin_delay[4:0]
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 33 Philips Semiconductors REGISTER OI_PCD OI_PDD OI_PED OI_PFD OI_CTRL0 OI_CTRL1 OI_BOC_R OI_BOC_G OI_BOC_B OI_BLC_R OI_BLC_G OI_BLC_B OI_G0ASX_HI OI_G0ASX_LO OI_G0ASY_HI OI_G0ASY_LO OI_G0AEX_HI OI_G0AEX_LO OI_G0AEY_HI OI_G0AEY_LO OI_G0AC OI_G0BSX_HI OI_G0BSX_LO OI_G0BSY_HI OI_G0BSY_LO OI_G0BEX_HI OI_G0BEX_LO OI_G0BEY_HI OI_G0BEY_LO ADR R/W 26H W 27H W 28H W 29H W 2AH W 2BH W 2CH W 2DH W 2EH W 2FH W 30H W 31H W 32H W 33H W 34H W 35H W 36H W 37H W 38H W 39H W 40H W 41H W 42H W 43H W 44H W 45H W 46H W 47H W 48H W RESET 0000 0000 0000 0000 0000 0000 0000 0000 -10- 0100 -000 0000 00H FFH 00H FFH 00H 00H ---- -000 01H ---- -000 01H ---- -000 25H ---- -000 02H ---- 0100 ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H point2_y[7:0] point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] point2_y[7:0] pol_CSG 0A+0B frame/line point2_ tog/reset point1_ tog/set point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] D7 pin_drv_pc[2:0] pin_drv_pd[2:0] pin_drv_pe[2:0] pin_drv_pf[2:0] ivsl1 ivsl0 D6 D5 D4 pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] 0 OI_enable power_ down double_ pixel blank_ mode PCLK_pol D3 D2 D1 D0
XGA analog input flat panel controller
PCLK_pin_delay[4:0] border_colour_red[7:0] border_colour_green[7:0] border_colour_blue[7:0] blank_colour_red[7:0] blank_colour_green[7:0] blank_colour_blue[7:0]
point1_x[10:8]
point1_x[10:8]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 34 Philips Semiconductors REGISTER OI_G0BC OI_G0BD OI_G1ASX_HI OI_G1ASX_LO OI_G1ASY_HI OI_G1ASY_LO OI_G1AEX_HI OI_G1AEX_LO OI_G1AEY_HI OI_G1AEY_LO OI_G1AC OI_G1BSX_HI OI_G1BSX_LO OI_G1BSY_HI OI_G1BSY_LO OI_G1BEX_HI OI_G1BEX_LO OI_G1BEY_HI OI_G1BEY_LO OI_G1BC OI_G1BD OI_G2SX_HI OI_G2SX_LO OI_G2SY_HI OI_G2SY_LO OI_G2EX_HI OI_G2EX_LO OI_G2EY_HI OI_G2EY_LO ADR R/W 49H W 4AH W 51H W 52H W 53H W 54H W 55H W 56H W 57H W 58H W 59H W 61H W 62H W 63H W 64H W 65H W 66H W 67H W 68H W 69H W 6AH W 71H W 72H W 73H W 74H W 75H W 76H W 77H W 78H W RESET ---- -000 X000 0000 pin_drv_csg0[2:0] ---- -000 03H ---- -000 01H ---- -000 05H ---- -000 46H ---- 0000 ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 X000 0000 pin_drv_csg1[2:0] ---- -000 06H ---- -000 05H ---- -000 56H ---- -000 40H point2_y[7:0] point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] pin_delay[4:0] point1_x[10:8] point2_y[7:0] frame/line point2_ tog/reset point1_ tog/set point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] point2_y[7:0] pol_CSG 1A+1B frame/line point2_ tog/reset point1_ tog/set point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] pin_delay[4:0] point1_x[10:8] D7 D6 D5 D4 D3 D2 frame/line D1 point2_ tog/reset D0 point1_ tog/set
XGA analog input flat panel controller
point1_x[10:8]
SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 35 Philips Semiconductors REGISTER OI_G2C OI_G2D OI_G3SX_HI OI_G3SX_LO OI_G3SY_HI OI_G3SY_LO OI_G3EX_HI OI_G3EX_LO OI_G3EY_HI OI_G3EY_LO OI_G3C OI_G3D OI_G4SX_HI OI_G4SX_LO OI_G4SY_HI OI_G4SY_LO OI_G4EX_HI OI_G4EX_LO OI_G4EY_HI OI_G4EY_LO OI_G4C OI_G4D OI_G5SX_HI OI_G5SX_LO OI_G5SY_HI OI_G5SY_LO OI_G5EX_HI OI_G5EX_LO OI_G5EY_HI ADR R/W 79H W 7AH W 81H W 82H W 83H W 84H W 85H W 86H W 87H W 88H W 89H W 8AH W 91H W 92H W 93H W 94H W 95H W 96H W 97H W 98H W 99H W 9AH W A1H W A2H W A3H W A4H W A5H W A6H W A7H W RESET ---0 1000 X000 0000 pin_drv_csg2[2:0] ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H ---- 0000 X000 0000 pin_drv_csg3[2:0] ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H ---0 0000 X000 0000 pin_drv_csg4[2:0] ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point2_y[7:0] invol_ CSG5 pol frame/line point2_ tog/reset point1_ tog/set point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] point2_y[7:0] pol pin_delay[4:0] point1_x[10:8] frame/line point2_ tog/reset point1_ tog/set point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] D7 D6 D5 D4 invol_ CSG3 pol D3 D2 frame/line D1 point2_ tog/reset D0 point1_ tog/set
XGA analog input flat panel controller
pin_delay[4:0] point1_x[10:8]
pin_delay[4:0] point1_x[10:8]
SAA6713AH
Product specification
point1_y[10:8]
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 36 Philips Semiconductors REGISTER OI_G5EY_LO OI_G5C OI_G5D OI_G6SX_HI OI_G6SX_LO OI_G6SY_HI OI_G6SY_LO OI_G6EX_HI OI_G6EX_LO OI_G6EY_HI OI_G6EY_LO OI_G6C OI_G6D OI_G7SX_HI OI_G7SX_LO OI_G7SY_HI OI_G7SY_LO OI_G7EX_HI OI_G7EX_LO OI_G7EY_HI OI_G7EY_LO OI_G7C OI_G7D OI_G8SX_HI OI_G8SX_LO OI_G8SY_HI OI_G8SY_LO OI_G8EX_HI OI_G8EX_LO ADR R/W A8H W A9H W AAH W B1H W B2H W B3H W B4H W B5H W B6H W B7H W B8H W B9H W BAH W C1H W C2H W C3H W C4H W C5H W C6H W C7H W C8H W C9H W CAH W D1H W D2H W D3H W D4H W D5H W D6H W RESET 00H ---- 0000 X000 0000 pin_drv_csg5[2:0] ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H ---- 0000 X000 0000 pin_drv_csg6[2:0] ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H ---- 0000 X000 0000 pin_drv_csg7[2:0] ---- -000 00H ---- -000 00H ---- -000 00H point2_x[7:0] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] point2_y[7:0] pol pin_delay[4:0] point1_x[10:8] frame/line point2_ tog/reset point1_ tog/set point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] point2_y[7:0] pol pin_delay[4:0] point1_x[10:8] frame/line point2_ tog/reset point1_ tog/set point2_x[7:0] point2_y[10:8] point1_y[7:0] point2_x[10:8] point1_x[7:0] point1_y[10:8] D7 point2_y[7:0] pol pin_delay[4:0] point1_x[10:8] frame/line point2_ tog/reset point1_ tog/set D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller SAA6713AH
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 37 Philips Semiconductors REGISTER OI_G8EY_HI OI_G8EY_LO OI_G8C OI_G8D OI_G8SPX_HI OI_G8SPX_LO OI_G8SPY_HI OI_G8SPY_LO OI_G9SX_HI OI_G9SX_LO OI_G9SY_HI OI_G9SY_LO OI_G9EX_HI OI_G9EX_LO OI_G9EY_HI OI_G9EY_LO OI_G9C OI_G9D OI_G9SPX_HI OI_G9SPX_LO OI_G9SPY_HI OI_G9SPY_LO OI_PWM0 OI_PWM1 OI_FCR OI_FCG OI_FCB OI_FC_EN ADR R/W D7H W D8H W D9H W DAH W DBH W DCH W DDH W DEH W E1H W E2H W E3H W E4H W E5H W E6H W E7H W E8H W E9H W EAH W EBH W ECH W EDH W EEH W F0H W F1H W F2H W F3H W F4H W F5H W RESET ---- -000 00H 0000 0000 point2_y[7:0] skip_mode point3_ toggle point3_ on/off point3_ frm/line pol frame/line point2_ tog/reset point1_ tog/set D7 D6 D5 D4 D3 D2 point2_y[10:8] D1 D0
XGA analog input flat panel controller
X000 0000 pin_drv_csg8[2:0] ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H ---- -000 00H 0000 0000 point2_y[7:0] skip_mode point3_ toggle point3_ on/off point2_x[7:0] point1_y[7:0] point1_x[7:0] point3_y[7:0] point3_x[7:0]
pin_delay[4:0] point3_x[10:8] point3_y[10:8] point1_x[10:8] point1_y[10:8] point2_x[10:8] point2_y[10:8] point3_ frm/line pol frame/line point2_ tog/reset point1_ tog/set
X000 0000 pin_drv_csg9[2:0] ---- -000 00H ---- -000 00H 00H ---X X000 00H 00H FFH ---- ---0 frame_col[23:16] frame_col[15:8] frame_col[7:0] point3_y[7:0] PWM[7:0] point3_x[7:0]
pin_delay[4:0] point3_x[10:8] point3_y[10:8]
PWM_HS_ PWM_pol sync
PWM_DIV[2:0]
SAA6713AH
Product specification
enable_ frame_ generator
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 Apr 05 38 Philips Semiconductors REGISTER OI_PWMD OI_WC OI_PCLKD Note 1. X = don't care. ADR R/W F6H W F6H R F7H W RESET 000- ---- 00H 0000 00-- D7 wait_count[7:0] pin_drv_pclk[2:0] pin_drv_outen[2:0] D6 D5 D4 D3 D2 D1 D0
XGA analog input flat panel controller
pin_drv_pwm[2:0]
SAA6713AH
Product specification
Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.2 Device ID 7.4 Clock management
SAA6713AH
The readable parameter device_id contains the IC version code. The current version returns the code 131CH. 7.3 Initialization
All clock management configuration registers are mapped to register page 0. A block diagram of the clock distribution is given in Fig.5. The clock source for the decoupling FIFO is selected by fifo_fclk. If fifo_fclk is set to logic 1, the front-end clock is applied to the decoupling FIFO; otherwise the back-end clock is used. The decoupling FIFO always has to be supplied with the clock signal of the higher clock rate.
The external Power-on reset is active LOW and applied to pin RST. Front-end, back-end and the output interface can be switched into the reset state individually by the I2C-bus programming using reset_fclk, reset_bclk and reset_oif at register GC_RESET (FCH). Each domain reset is active if the corresponding programming bit is set to logic 1.
handbook, full pagewidth
vclk_in_en HS_PLL VS_PLL LINE-LOCKED PLL 0
line_pll_phase [4:0]
PHASE SHIFT 1
ADC sample clock
configuration signals VCLK (I/O)
configuration signals bclk_in_en
vclk_in_en
0 CLK PANEL CLOCK PLL 0 1 1 frontend_bclk back-end clock 0 front-end clock
/4
system clock 1 clk_div4
/2
0 configuration clock 1 cfgclk_select
MHC279
Fig.5 Clock distribution.
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.4.1 CLOCK SIGNALS
SAA6713AH
An externally generated clock signal can also be connected to pin VCLK if vclk_in_en is set to logic 1. Alternatively, the back-end clock can be selected as front-end clock, which is particularly needed if the picture generator is used without an external clock source. Front-end clock modes are shown in Table 20. Table 20 Front-end clock switching modes; note 1 frontend_ FRONT-END vclk_in_en DESCRIPTION bclk CLOCK 1 0 0 X 1 0 back-end clock VCLK line PLL clock initialization external clock generation internal clock generation
7.4.1.1
System clock
The system clock is applied to pin CLK and is used to drive the internal control structures and block configuration, and serves as input for the panel clock PLL. The maximum clock rate is 50 MHz. The system clock is directly taken from pin CLK if clk_div4 is set to logic 0; otherwise the system clock is derived from the clock signal at pin CLK additionally divided by 4 as shown in Table 18. Table 18 System clock switching modes clk_div4 0 1 SYSTEM CLOCK CLK
1 4CLK
DESCRIPTION direct input divided by 4 Note 1. X = don't care.
7.4.1.2
Back-end clock
The back-end clock is the pixel clock used in data processing behind the decoupling FIFO. Possible clock rates lie between 5 and 100 MHz in case of single pixel panel output, but it is identical with the panel clock; if using double pixel mode it equals twice the panel clock. The clock signal is generated by the panel clock PLL based on the system clock if bclk_in_en is set to logic 0; otherwise the signal applied externally to pin CLK is used as system clock (see Table 19). Table 19 Back-end clock switching modes bclk_in_en 1 0 BACK-END CLOCK CLK PLL clock DESCRIPTION external clock internal clock generation
7.4.1.4
Configuration clock
The internal configuration clock is driving the configuration parameters section of all modules. It is usually running at half the back-end clock frequency. If somehow the back-end clock is not usable for the configuration, the system clock could be used to drive the configuration clock instead. The selection of the configuration clock source could either be done automatically monitoring the back-end clock or forced manually if this is desired. For power saving issues the configuration clock is powered-down during inactive periods when no data is received or requested via the I2C-bus interface. See Table 21 for configuration clock switching options. Table 21 Configuration clock switching modes cfgclk_select CONFIGURATION CLOCK half back-end clock DESCRIPTION application (stable back-end clock) initialization
7.4.1.3
Front-end clock
0
The front-end clock is the pixel clock of the input section and is generated by the line PLL for the analog RGB input. The front-end clock rate can be up to 110 MHz. Pin VCLK is switched as output for the used clock signal.
1
CLK
2004 Apr 05
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.4.2 CLOCK ACTIVATION CONTROL
SAA6713AH
The PLLs are activated by pll_en and line_pll_en and the back-end clock PLL pre-divider by pll_pre_div_en at register CD_PLL_CTRL (20H). Bits line_pll_vs_pol and line_pll_hs_pol define the polarity of the vertical and horizontal sync inputs. Each bit has to be set to logic 1 in case of positive (active HIGH) polarity of the corresponding sync signal; otherwise to logic 0. The outputs for the pre-divider, n-divider and m-divider ratios are set accordingly to bits pll_pre_div, pll_m_div, pll_n_div, line_pll_m_div and line_pll_n_div at registers CD_PLL_P_HI to CD_LPLL_LO (21H to 26H). The pll_n_div is a programmable divider between 100 to 4096. The relation between hsync and pll_clk is: pll_clk = pll_n_div x hsync. The frequency of the oscillator should be selected at minimum two times pll_clk. The pll_m_div is a programmable divider between `00' = 1, `01' = 2, `10' = 2, `11' = 4 and limits the current controlled oscillator tuning range. The line PLL clock is finally phase shifted as defined in steps of 11.25 degrees by line_pll_phase at register CD_LPLL_PHA (27H). For the auto-adjustment phase distortion measurement register CD_LPLL_PD contains an alternative phase value pd_pll_phase for the line PLL. Parameter phase_auto enables switching between both phase values controlled by the auto-adjustment if set to logic 1, or manual selection by phase_select.
The clock signals of auto-adjustment, downscaler, upscaler and OSD module are powered-down automatically during inactivity if programming bits aaclk_auto, dscclk_auto, uscclk_auto and osdclk_auto respectively in register CD_CLK_AUTO (11H) are set to logic 1. Otherwise the clock signals are switched on and off according to the state of bits aaclk_on, dscclk_on, uscclk_on and osdclk_on respectively in register CD_CLK_EN (10H). The general configuration and the OSD configuration clock signal are also powered-down during inactivity unless forced active, when cfgclk_on or osd_cfgclk_on respectively (CD_CLK_EN, 10H) is set to logic 1. When automatic activation is selected, each clock signal is active during either power-on or the programmable reset of the specific domain and whenever the concerned module is activated. 7.4.3 PLL PROGRAMMING
The SAA6713AH contains two PLLs: * Line-locked PLL generating the sample clock from the hsync signal (see Fig.6) * PLL running on the system clock generating the panel clock (see Fig.7). The PLL programming registers are mapped to register page 0.
handbook, full pagewidth
line_vs_pol
line_hs_pol
line_pll_en
line_pll_m_div [1:0]
HS_PLL VS_PLL
FREQUENCY AND PHASE DETECTOR
OSCILLATOR 50 to 320 MHz
m-DIVIDER
/2
line PLL clock
n-DIVIDER
MHC215
line_pll_n_div [11:0]
Fig.6 Line PLL block diagram.
2004 Apr 05
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
pll_pre_div [15:0] FREQUENCY AND PHASE DETECTOR
pll_en
pll_m_div [1:0]
CLK
PRE-DIVIDER
OSCILLATOR 50 to 320 MHz
m-DIVIDER
/2
PLL clock
pll_pre_div_en n-DIVIDER
MHC214
pll_n_div [11:0]
Fig.7 PLL block diagram.
7.5
Synchronization pulse distribution
The line-locked PLL, input interface and mode detection are provided with horizontal and vertical synchronization pulse signals (HSYNC and VSYNC). Signal switching is controlled by configuration registers SYNC_SEL (18H at page 0) and SYNC_DIS (19H at page 0). A composite sync decoder and hsync regeneration can be inserted. Possible selections and the concerned configuration parameters are shown in Fig.8 and described more detailed in the Sections 7.5.1 to 7.5.5. 7.5.1 COMPOSITE SYNC INPUT
To provide a stable hsync during the vsync, the sync-on-green slicer might have to be disabled during the vsync which is performed automatically if sog_vs_disable is set to logic 1; otherwise the sync-on-green slicer is constantly enabled. The composite sync decoder will regenerate hsync and vsync signals for internal use. Figure 9 shows the composite sync modes that can be used. The maximum number of equalizing pulses (csync-3 and csync-4) may not exceed 30. Table 22 Composite sync decoder input selection sog_en 1 0 SOG HSYNC CSYNC
The composite sync decoder input is selected by sog_en between the separated SOG provided by the sync-on-green slicer and a composite sync applied at input pin HSYNC (see Table 22). The sync-on-green slicer has to be enabled by setting sync_on_green_en in register ADC_CTRL (00H at page 1) to logic 1.
2004 Apr 05
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
mdd_cs_sog_en HSYNC 0 1 1 mdd_hs_regen_on HSYNC 0 1 1 iif_cs_sog_en 0 HSYNC REGENERATION HSYNC 1 HSYNC 0 HS_PLL 1 iif_cs_sog_en iif_hs_regen_on HS_REGEN 0 HS_IIF 0 HS_MDD
ACTIVITY DETECTION
hs_regen_in_en sog_en HSYNC SOG 0 CSYNC 1 HS_CS COMPOSITE SYNC DECODER
VS_CS
VSYNC ACTIVITY DETECTION
0 VS_MDD 1
ACTIVITY DETECTION VSYNC
mdd_cs_sog_en
0 VS_IIF 1 VSYNC ACTIVITY DETECTION 0 iif_cs_sog_en VS_PLL 1 iff_cs_sog_en
MHC280
Fig.8 Synchronization pulse distribution.
2004 Apr 05
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth hsync
vsync
csync-1
csync-2
csync-3
csync-4
csync-5
MHC217
Fig.9 Supported composite sync modes.
7.5.2
HSYNC REGENERATION
7.5.4
SELECTION OF SYNCS FOR MODE DETECTION AND
INPUT INTERFACE
The hsync regeneration reproduces a regular hsync, e.g. in case of equalizing pulses or an absent hsync during vsync. The input selection is shown in Table 23. Table 23 Hsync regeneration input selection hs_regen_in_en 0 1 7.5.3 HS_CS HSYNC HS_REGEN
The output selection for input interface and mode detection allows to choose between the input signals HSYNC and VSYNC, composite sync decoder outputs HS_CS and VS_CS. The regenerated hsync HS_REGEN can be selected as source (see Tables 25 and 26). Table 25 Mode detection sync selection; note 1 mdd_cs_ sog_en 0 1 1 Note 1. X = don't care. mdd_hs_ regen_on X 0 1 HS_MDD HSYNC HS_CS HS_REGEN VS_MDD VSYNC VS_CS
SELECTION OF SYNCS FOR LINE-LOCKED PLL
The source signals of the line-locked PLL are selected according to Table 24 as either HSYNC and VSYNC from the input pins or the composite sync decoder outputs HS_CS and VS_CS. Table 24 Line-locked PLL sync selection iif_cs_sog_en 0 1 HS_PLL HSYNC HS_CS VS_PLL VSYNC VS_CS
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
Table 26 Input interface sync selection; note 1 iif_cs_sog_en 0 1 1 Note 1. X = don't care. 7.5.5 PIN VSYNC CONFIGURATION iif_hs_ regen_on X 0 1 HS_IIF HSYNC HS_CS HS_REGEN int_fifo int_osd int_oif int_iif VS_IIF VSYNC VS_CS int_auto
SAA6713AH
Table 28 Interrupt conditions and description INTERRUPT int_mode SUBMODULE mode detection DESCRIPTION change of input video mode detected
auto-adjustment auto-adjustment finished decoupling FIFO OSD output interface input interface FIFO overflow end of programmed OSD frame sequence FIFO underflow line jitter occurs (hsync jitter detection)
Besides serving as input for an external vertical synchronization pulse VSYNC can be switched as output of the vsync internally derived from (not shown in Fig.8): * Sync-on-green slicer (SOG) * Composite sync decoder (VS_CS). The I/O direction of pin VSYNC is selected by vsync_out_en of register SYNC_SEL (18H at page 0). In case of output mode, the source is selected by sog_out_en of register SYNC_SEL according to Table 27. Table 27 Pin VSYNC switching modes; note 1 vsync_out_en sog_out_en DIRECTION 0 1 1 Note 1. X = don't care. 7.6 Interrupt generation X 1 0 input output VSYNC external SOG VS_CS
Interrupt output pin INT is set LOW (active) whenever one or more of the interrupt flags is HIGH. The interrupt flags are set HIGH, when the corresponding interrupt condition is met: * The mode detection interrupt flag is set HIGH when one of the mode measurement bits toggles or a value changes significantly at the vsync or in case of vsync or hsync jitter, depending on which of the conditions are enabled (see Section 7.10.1). * The auto-adjustment interrupt flag is set HIGH in the moment an auto-adjustment measurement finishes, indicating the result values can be read out. * The decoupling FIFO interrupt flag is set HIGH whenever the decoupling FIFO is full, indicating that the output timing is too slow and a change of the timing is required; otherwise a corrupt output picture will occur. * The OSD interrupt flag is set HIGH every time a pointer animation frame sequence ends to allow to switch the displayed icon and program the icon for the next turn (see Section 7.13.3). * The output interface interrupt flag is set HIGH when the pixel stream to the output interface is broken, indicating that the output pixel or line rate is too fast. * The hsync jitter interrupt flag (int_iif) is set HIGH when line jitter at the analog video input occurs more than a number of times specified in the register II_HJIT, indicating that the other clock edge should be used to sample the hsync and vsync signal.
An interrupt signal is provided at output pin INT (active LOW). The state of INT is based on mode detection, auto-adjustment, OSD, decoupling FIFO and output interface interrupt conditions shown in Table 28.
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Product specification
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The interrupt flags are accessible at the global interrupt state register GC_INT_STAT (FEH) and are readable. The flags are only cleared (set to LOW) if a logic 1 is written into the corresponding bit in GC_INT_STAT. The interrupt conditions are maskable by the corresponding programming bit in GC_INT_MASK (FDH); a logic 1 is enabling the particular interrupt condition. 7.7 Triple analog-to-digital converter
SAA6713AH
allowed. These combinations would result in a very low input DC level, which would result in the clamp circuit going out of saturation. This would lead to unpredictable behaviour of the clamp level. The allowed region for the gain value is limited between 27 and 110. The clamp and gain correction pulse generation is programmed via registers II_ADC_CTRL and II_CLAMP_ON to II_GAINC_OFF (02H to 06H at page 4). Clamp pulse generation is enabled by clamp_en. The beginning of the clamp pulse CLAMP is marked by clamp_on_delay as an offset to the second edge of the hsync pulse, the end by clamp_off_delay as shown in Fig.10. The polarity of CLAMP is given with clamp_pol; logic 1 is HIGH active and logic 0 is LOW active. During the clamp pulse, that should fall into the hsync backporch, the ADCs each match the sampled black level output value to the value given by adc_red_brightness, adc_green_brightness and adc_blue_brightness respectively. The gain correction pulse GAINC is the delayed hsync. The first edge of the hsync is delayed by gainc_on_delay and the second edge by gainc_off_delay (see Fig.10). The polarity is programmed by gainc_pol; logic 1 is HIGH active and logic 0 is LOW active. The gain correction pulse generation is enabled by setting gainc_en. During gain correction the ADC inputs are connected to a reference voltage and by gain adjustment the output is matched to adc_red_contrast, adc_green_contrast and adc_blue_contrast.
The integrated triple ADC samples analog RGB signals of up to 110 MHz with a resolution of 8 bits per colour component and provide automatic brightness and contrast control (see Fig.11). The sample clock is generated by the line-locked PLL (see Section 7.4.3), but can also be applied externally. The triple ADC is automatically enabled, when analog RGB is selected as input source. The time frames for the ADC automatic brightness and gain control are defined by clamp and gain correction pulses generated by the input interface. During these times the ADCs adjust brightness and gain according to the programmable brightness and contrast values defined by adc_red_brightness to adc_blue_contrast at registers ADC_R_BRI to ADC_B_CON (01H to 06H at page 1), that have to be provided in 2s-complement form between -128 (80H) and +127 (7FH). Not all combinations of contrast and brightness settings are allowed. Combining very low contrast (low gain) together with low brightness (more black than black) is not
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VHS
clamp_off_delay clamp_on_delay RGB data
GAINC
gainc_on_delay CLAMP
gainc_off_delay
MHC218
Fig.10 Gain adjustment and clamp pulse generation.
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Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
ANALOG PART RBIAS BIAS AND REFERENCE TIMING
DIGITAL PART clamp pulse ADC clock gain pulse brightness setting (8-bit) blue channel output (8-bit) contrast setting (8-bit) sync output SOG enable brightness setting (8-bit) green channel output (8-bit) contrast setting (8-bit)
R1 blue R1 0.75 R1
C1 AGC
CLAMP
C1
ADC
CSOG SYNC-ON-GREEN
R1 green R1 0.75 R1
C1 AGC
CLAMP
C1
ADC
R1 red R1 0.75 R1
C1 AGC
CLAMP
brightness setting (8-bit) red channel output (8-bit) contrast setting (8-bit)
C1
ADC
MHC219
Fig.11 Analog video input block diagram.
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.8 Input interface 7.8.2 SYNCHRONIZATION SIGNALS
SAA6713AH
The input interface selects video data either provided by the ADCs or externally applied and extracts the input picture for processing. The sample window position and size is programmable, using vertical and horizontal synchronization signals as reference. Alternatively, the picture generator can generate different test pictures with programmable size and horizontal and vertical blanking length. All input interface programming registers are mapped to the I2C-bus configuration register page 4. 7.8.1 INPUT SELECTION
The synchronization pulses are used to identify the frame outline. The sync signals for the input interface are provided by the sync distribution. The complete description of sync switching options is given in Section 7.5. If analog or parallel RGB input mode is used, the vertical synchronization pulse (vsync) is connected to pin VSYNC and the horizontal synchronization pulse (hsync) to pin HSYNC. A composite synchronization signal is connected to pin HSYNC. Pin VSYNC can then serve as an output for the generated vertical synchronization pulse. The polarities of hsync and vsync are defined by vs_pol and hs_pol. In case of active HIGH polarity, the corresponding bit has to be set to logic 1; otherwise to logic 0. If sync_clk_edge is set to logic 1 all synchronization signals are sampled with the rising front-end clock signal edge; otherwise with falling edge. If delay_vs is set to logic 1, the vsync is delayed in relation to the hsync to prevent line jitter if both occur at the same time, which is monitored by the mode detection. 7.8.3 DEFINITION OF SAMPLE WINDOW
The input source is selected by ext_select (register II_CTRL, address 00H) as shown in Table 29. In case of parallel RGB input, the R component has to be provided at ports PA7 (MSB) to PA0 (LSB) in 8-bit format (range 0 to 255), G and B component similarly at ports PB7 to PB0 and ports PC7 to PC0, respectively. The input source can only be changed in a functional reset (see Section 7.3). The clock signal edge used to sample the data inputs is specified by ext_clk_edge. If ext_clk_edge is set to logic 1 data is sampled on the rising front-end clock edge; otherwise on the falling front-end clock edge. If convert_2s is set to logic 1 the incoming data is expected to be in 2s-complement form from -128 (80H) to +127 (7FH); otherwise input data is treated as unsigned values from 0 to 255. Data from the internal ADCs is always in 2s-complement form. To enable the input interface in_form_on has to be set to logic 1; otherwise no data will be provided for processing. If the picture generator is active, the input formatter will always provide generated data. Table 29 Input source selection ext_select 1 0 INPUT SOURCE parallel RGB analog RGB
The sample window is defined by in_v_offset, in_h_offset, in_v_length and in_h_length. The vertical offsets are measured from the trailing edge of the vsync pulse. The horizontal offsets are measured from either the first edge of the hsync pulse if hsync_edge is set to logic 1, or the second edge if hsync_edge is set to logic 0. Figure 12 shows the horizontal offset for the case hsync_edge is set to logic 0. If both offsets are set to value 0H, sampling will start with the first pixel in the first line (see Fig.13). The length defines width and height of the sampled frame. The vertical sample offset and length are given in lines and the horizontal offset and length are measured in pixels.
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Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
VHS
h_offset n 0 1 23 4 5
h_length
RGB data
MHB253
Fig.12 RGB data sampling (hsync_edge = 0).
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VCLK
HSYNC
PA, PB, PC
X
0
1
2
3
4
5
6
X
in_h_offset
in_h_length
MHC220
Fig.13 RGB input port timing using a data enable signal (connected to HSYNC).
7.8.4
INTERLACED INPUT
7.8.5
PICTURE GENERATOR
Sampling of interlaced RGB data is enabled by interlace_on. The polarity of the input fields is determined by the number of hsyncs within a frame. The even fields are expected to contain an additional line if reverse_field_id is set to logic 0, or to contain one line less if reverse_field_id is set to logic 1. In the interlaced input mode, the vertical sampling length parameter in_v_length has to be programmed with the length of the actual field (is half the frame length). For de-interlacing, the upscaler has to be programmed accordingly.
The input interface contains a picture generator, that can be used to apply simple test pictures instead of using the ADC. A front-end clock has to be provided (see Section 7.4.1). The picture generator is active when test_pic_on is logic 1. It generates a picture of the size defined by in_h_length and in_v_length with additional blanking. The total line length and number of lines are defined by h_length_total and v_length_total. The input interface sample offset is without effect when using the picture generator.
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Product specification
XGA analog input flat panel controller
The picture generator consists of a border generation, a vertical and a horizontal ramp and ripple generator, that work independently. The two ramp and ripple generators can be activated separately for each RGB colour component. If h_ramp_r, h_ramp_g, h_ramp_b, v_ramp_r, v_ramp_g or v_ramp_b are set to logic 1, the corresponding ramp and ripple pattern is applied to the corresponding colour component; otherwise the pattern does not contribute to the colour component. If white_border is logic 1, then the border generator is activated for all colours. The border, horizontal and vertical ramp and ripple generator outputs are added up for each colour component. Additionally, all colour components are bit reversed if invert is set to logic 1. Both ramp and ripple pattern generators work in the same way, only the horizontal generator is based on the column position and the vertical generator on the line number. The ramp and ripple generation is shown in Fig.14 for the example of the horizontal generator. The first step size (h_step1 or v_step1) defines the interval after which the increment value (h_colour_inc or v_colour_inc) is added to the current colour. If the second step size (h_step2 or v_step2) is set to 0, the increment is repeatedly added after the first step size interval. If the second step size is not 0, after the increment value was added the second step size defines the position where the decrement value is subtracted from the current colour. After this the first step size and the increment is applied again and so on. Range over or underflows are not suppressed and cause the colour values to wrap around. 7.8.6 HSYNC JITTER DETECTION
SAA6713AH
For certain sampling phases the hsync is sampled at its edge and thus unstable. This jitter is detected and another sampling clock edge can be used to avoid it. To detect hsync sample jitter the interval between hsyncs in sample clock cycles is monitored. If the length varies, hsync jitter is detected. As the sample jitter can only change the line length by a maximum of two cycles, only the lowest two bits of the line length have to be considered. If the current line length differs from the previous line, line jitter occurred. The differences of line lengths within a frame are accumulated and the hsync jitter interrupt may be generated when a certain level (hs_jitter_th) is exceeded. During normal operation the jitter detection is only active during the sampled area of the input frame, because the clock rate of the PLL generated sample clock might slightly vary during vsyncs. The detection circuit is active at all times during reset or when the input interface is disabled. For the interrupt a state and an enable register exists, as well as a clear flag. The interrupt is level-based, so every frame after a certain number of occurrences until the next vsync the interrupt state is set to logic 1. The jitter detection does not work correctly without a vsync signal.
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255
h_step1
h_step2
h_colour_dec colour value h_colour_inc
wrap around
0 column position
MHC221
Fig.14 Picture generator ramp and ripple pattern (horizontal generator).
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.9 Colour processing
SAA6713AH
The source of the synchronization pulse signals used by the mode detection is selected by the sync distribution as described in Section 7.5.4 (HS_MDD and VS_MDD). The absence of synchronization pulses is indicated by the flags no_vsync and no_hsync. If the corresponding synchronization signal cannot be detected, the flags are set to logic 1; otherwise to logic 0. It should be noted that the hsync is considered undetected, whenever there are more than 65536 back-end clock cycles between two hsyncs. The bits vsync_pol and hsync_pol provide the polarities of the synchronization signals applied. If the synchronization signal is active HIGH, the corresponding flag is set to logic 1; otherwise the flag is set to logic 0. The flag jitter_detected is set to logic 1, when the active edge of hsync and vsync coincide indicating a possible jitter of the syncs, which would lead to an incorrect or unstable result for the number of hsyncs between vsyncs; otherwise the flag is set to logic 0. If a possible jitter between hsync and vsync is detected, a delayed vsync can be used for the measurements instead, which is selected by setting delay_vsync to logic 1; otherwise the original vsync is used. The value of v_lines reports the number of lines within a frame up to a maximum of 2048 lines and v_clocks gives the length of the input frame in back-end clock cycles with a maximum of 224 clock cycles. The horizontal period in back-end clock cycles is given by h_clocks, which can be determined in different measurement modes. If h_clocks_accu and h_clocks_cont are both set to logic 0, the h_clocks value is determined once per frame in the middle of the frame. If h_clocks_accu is logic 1, then h_clocks gives the accumulated length of 16 lines also measured in the middle of the frame. If h_clocks_accu is logic 0, but h_clocks_cont is set to logic 1, then the h_clocks measurement is performed every line of the frame, including the vertical blanking and vsync time. The maximum horizontal period is 65536 back-end clock cycles. The measurement results can be used to generate a mode detection interrupt. Each flag or value can be individually enabled for interrupt generation by setting the corresponding interrupt enable bit jitter_int_en, v_lines_int_en, h_clocks_int_en, v_clocks_int_en, no_vsync_int_en, no_hsync_int_en, vsync_pol_int_en or hsync_pol_int_en to logic 1. Changes of v_lines, v_clocks and h_clocks only cause an interrupt if the difference between new and old value is greater than four.
The colour processing performs brightness and contrast adjustment. A programmable offset and gain factor is applied to each RGB colour component. Additional gain and offset values can be applied to the pixel data, not affecting R, G and B components separately, but all components at the same time. Luminance and chrominance of the pixel data can be directly adjusted, which allows true brightness, contrast and colour saturation using single parameters. Register CP_GAIN_Y controls the contrast and CP_OFFS_Y controls the brightness level; both without affecting the colour temperature. Registers CP_GAIN_CB, CP_OFFS_CB, CP_GAIN_CR and CP_OFFS_CR specify gain and offset values for the red and blue saturation of the RGB data. The colour saturation can be shifted simply by using both gain values. The gain and offset values are specified by the 8-bit configuration registers CP_GAIN_Y to CP_OFFS_B (address 00H to 0BH at page 5). The offset values offset_y, offset_cb and offset_cr for Y-CB-CR and offset_r, offset_g and offset_b for RGB colour space are given in the range from -128 (80H) to +127 (7FH) in 2s-complement form. The gain factors gain_y, gain_cb and gain_cr as well as gain_r, gain_g and gain_b are given in unsigned form, 128 (80H) representing a factor of 1.0. 7.10 RGB mode detection and auto-adjustment
The SAA6713AH can be used to build up auto-scan systems using an external microcontroller. Therefore, information about the input resolution and timing are measured by the SAA6713AH that can be read out via the I2C-bus. Provided information can be divided into mode detection information to determine the actual RGB input mode and various auto-adjustment features to support the adjustment of the setting of the SAA6713AH to the new mode. 7.10.1 MODE DETECTION
The mode detection determines mode characteristics of the selected video input. The information is provided at the readable I2C-bus registers and changes in the values can trigger the interrupt. All the mode detection I2C-bus registers are mapped to register page 2. The mode detection uses the back-end clock and cannot run without a present back-end clock. The mode detection is enabled by setting md_on to logic 1.
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Product specification
XGA analog input flat panel controller
Additionally, the mode detection interrupt can be generated on the falling edge of every vsync, which is enabled if vsync_int_en is set to logic 1. The states of each interrupt condition vsync_int, jitter_int, vsync_pol_int, hsync_pol_int, no_vsync_int, no_hsync_int, v_lines_int, h_clocks_int and v_clocks_int can be read out at registers MD_INT_HI and MD_INT_LO (0AH and 0BH). Whenever an interrupt condition is met, the particular flag is set to logic 1. If clear_int at MD_CTRL (00H) is programmed with logic 1, all interrupt flags are cleared. If int_lock is set to logic 1, all flags and values are frozen in the moment an interrupt occurs until clear_int is set to logic 1 the next time. 7.10.2 SYNC ACTIVITY DETECTION 7.10.3 AUTO-ADJUSTMENT
SAA6713AH
There are four auto-adjustment modes: * Active area detection * Brightest and lowest pixel search * Pixel measurement * Phase distortion measurement. The programming registers for all four modes are shared. Bit aa_mode selects the auto-adjustment mode according to Table 31. Table 31 Auto-adjustment modes aa_mode[1:0] 00 01 10 11 FUNCTION active area detection brightest and lowest pixel search pixel measurement phase distortion measurement
Activity detection for AVI horizontal and vertical sync is provided. Moreover, the vertical sync output of the CSYNC slicer and the sync-on-green signal from the sync separator are checked permanently for activity. An interrupt may be generated on any change of activity. Interrupts can be masked with a set of interrupt enable bits. Writing a logic 1 to the existing clear_int bit will clear this interrupts. For activity bits, logic 0 means inactive and logic 1 means active. For sync interrupt bits, logic 0 means disabled and logic 1 means enabled. For sync active interrupt bits, logic 0 means no interrupt and logic 1 means interrupt pending. The sync-on-green activity detection is only an indicator that the digital output of the sync slicer is active. The line-locked PLL with its lock flag should be used to distinguish a real sync-on-green from disturbances resulting from the image data on the green channel. Table 30 Line PLL lock llpll_inlock 0 1 FUNCTION line PLL out-of-lock line PLL in lock
In each mode, reference colours or reference coordinates have to be programmed (into bits ref_colour_0, ref_colour_1 or ref_row_0, ref_col_0, ref_row_1, ref_col_1 respectively). The auto-adjustment is activated by writing to the AA_CTRL register and started synchronized to the beginning of the next frame. The function is then applied for a number of frames defined in aa_cycles. After performing the auto-adjustment for this number of frames, an interrupt can be generated. The different aa-functions have two further aa_submode bits to control the functionality of each auto-adjustment mode.
7.10.3.1
Active area detection
With the active area detection feature it is possible to measure the number of blanking pixels and lines between the synchronization pulses and the active video. To distinguish between blanking and active video the threshold colour values ref_colour_0 and ref_colour_1 have to be defined. Parameter ref_colour_0 is used to determine the start of the active video area. If the sample value of at least one of the three colour components is above this value the pixel is treated as upper left corner of active video.
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Product specification
XGA analog input flat panel controller
Its coordinates are stored in eval_col_0 (x-coordinate) and eval_row_0 (y-coordinate). All pixels are also compared with the ref_colour_1 values. If one of the current colour values is bigger, the coordinates are saved in eval_row_1 and eval_col_1. At the end this value defines the lower, right corner of the active area. The values are kept in eval_row_0/1 and eval_col_0/1 until another mode or another area detection without resample is started. It is also possible to start measuring with the preceded values in the resample submodes. In submodes without resample, the results will not be smaller than the preceding values. There are two different modes available: * In the enhanced mode all input data is used for measurement (see Fig.15) * In the non-enhanced mode only one input line, defined by ref_row_1 and one input column, defined by ref_col_1, is used (see Fig.16). The needed sample offsets for the input interface can be directly obtained by reading out the eval_row_0 and eval_col_0 values. The number of active pixels per line and lines per field is generated by subtracting the eval_row_0, eval_col_0 value from the eval_row_1, eval_col_1 value. Dependent on the sampling settings of the input interface, the eval_row_0 and eval_col_0 values usually correspond to the horizontal and vertical backporch of the incoming video signal and the active video, of course, meets the active area of that stream. The calculated active pixels per line value can be used for adjusting the line-locked PLL which is generating the ADC sample clock in a way that this value matches the number of expected active pixels per line in the actual graphics mode. There are four submodes available, as shown in Table 32. In the non-enhanced modes, the active area detection is not performed over the whole frame as in the enhanced modes, but only within the line and within the column programmed by ref_row_0 and ref_col_0. For correct results, these reference values have to be previously set inside the active area of the picture. If a submode with initial values is selected eval_col_0/1 and eval_row_0/1 are reset to their initial values before evaluation. The brightest and lowest pixel value inside the active area is available in ref_pixel_red_0/1, ref_pixel_green_0/1 and ref_pixel_blue_0/1. The evaluated values for the lowest colour value pixel cannot be lower than the lowest threshold value.
Active area: shaded.
SAA6713AH
handbook, halfpage start
ref_colour_0 eval_row_0 > ref_colour_0 > ref_colour_1 eval_row_1 ref_colour_1
eval_col_0
eval_col_1
MHC222
Fig.15 Enhanced mode.
handbook, halfpage start
ref_col_1
ref_colour_0 >ref_colour_0 eval_row_0 ref_row_1
>ref_colour_1 ref_colour_1
eval_row_1
eval_col_0 Active area: shaded.
eval_col_1
MHC223
Fig.16 Non-enhanced mode.
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XGA analog input flat panel controller
Table 32 Mode 00 (active area detection) BIT Input values aa_submode[1:0] submode DESCRIPTION
SAA6713AH
00: enhanced mode with resampling, no initial values, evaluation over full frame 01: non-enhanced mode with resampling, no initial values, evaluation in one row and column 10: enhanced mode with initial values 11: non-enhanced mode with initial values aa_cycles[1:0] measurement interval 00: 1 frame 01: 4 frames 10: 8 frames 11: until next change in position value ref_col_0[10:0] ref_row_0[11:0] ref_colour_0[23:0] ref_colour_1[23:0] Output values eval_col_0[15:0] eval_row_0[15:0] eval_col_1[15:0] eval_row_1[15:0] ref_pixel_red_0[7:0] ref_pixel_blue_0[7:0] ref_pixel_red_1[7:0] ref_pixel_blue_1[7:0] active area upper left corner column; will be set to FFFF before evaluation in mode without resample active area upper left corner row; will be set to FFFF before evaluation in mode without resample active area lower right corner column; will be set to 0000 before evaluation in mode without resample active area lower right corner row; will be set to 0000 before evaluation in mode without resample maximum red component colour value over the whole frame maximum blue component colour value over the whole frame minimum red component colour value within active area minimum blue component colour value within active area reference column (for non-enhanced mode) reference row (for non-enhanced mode) threshold value of backporch colour (upper left) threshold value of frontporch colour (lower right)
ref_pixel_green_0[7:0] maximum green component colour value over the whole frame
ref_pixel_green_1[7:0] minimum green component colour value within active area
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.10.3.2 Brightest and lowest pixel search
SAA6713AH
The brightest and lowest pixel search determines the position of the brightest pixels and the lowest pixels in a predefined area. Therefore, the area is scanned from the upper left to the lower right corner. The pixel value and the position values are readable. Four submodes are available to search independently for RGB minimum and maximum values (see Table 33). Table 33 Mode 01 (minimum and maximum search) BIT Input values aa_submode[1:0] submode 00: maximum of red and green 01: maximum of blue 10: minimum of red and green 11: minimum of blue aa_cycles[1:0] measurement interval 00: 1 frame 01: 4 frames 10: 8 frames 11: 16 frames ref_col_0[10:0] ref_row_0[11:0] ref_col_1[10:0] ref_row_1[11:0] Output values eval_col_0[15:0] eval_row_0[15:0] eval_col_1[15:0] eval_row_1[15:0] ref_pixel_red_0[7:0] ref_pixel_blue_0[7:0] ref_pixel_red_1[7:0] ref_pixel_blue_1[7:0] pixel position 0 column (according to submode) pixel position 0 row (according to submode) pixel position 1 column (according to submode) pixel position 1 row (according to submode) red channel colour value at evaluated position 0 blue channel colour value at evaluated position 0 red channel colour value at evaluated position 1 blue channel colour value at evaluated position 1 search area upper left corner column search area upper left corner row search area lower right corner column search area lower right corner row DESCRIPTION
ref_pixel_green_0[7:0] green channel colour value at evaluated position 0
ref_pixel_green_1[7:0] green channel colour value at evaluated position 1
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.10.3.3 Pixel measurement
SAA6713AH
Three submodes are available to output the maximum value, the minimum value or the mean value at the dedicated position (see Table 34). To simplify the measurements, the values can be taken as a single snapshot representing the momentary value of the pixel at the reference position or they can be build up over several frames, which is activated by programming the number of frames to bits aa_cycles.
For exact measurements within the incoming video stream, two reference pixel positions can be defined with ref_row_0, ref_col_0 and ref_row_1, ref_col_1. The R, G and B components of this pixel are sampled and available at ref_pixel_red_0/1, ref_pixel_green_0/1 and ref_pixel_blue_0/1. The reference pixel colour values can be used for fine tuning the external PLL in frequency and phase and for colour gain adjustment. Table 34 Mode 10 (pixel measurement) BIT Input values aa_submode[1:0] submode
DESCRIPTION
00: maximum of pixel at dedicated positions 01: minimum of pixel at dedicated positions 10: mean value of pixel at dedicated positions 11: mean value of pixel at dedicated positions aa_cycles[1:0] measurement interval 00: 1 frame 01: 4 frames 10: 8 frames 11: 16 frames ref_col_0[10:0] ref_row_0[11:0] ref_col_1[10:0] ref_row_1[11:0] Output values ref_pixel_red_0[7:0] ref_pixel_blue_0[7:0] ref_pixel_red_1[7:0] ref_pixel_blue_1[7:0] red channel colour value at position 0 blue channel colour value at position 0 red channel colour value at position 1 blue channel colour value at position 1 ref_pixel_green_0[7:0] green channel colour value at position 0 pixel position 0 column pixel position 0 row pixel position 1 column pixel position 1 row
ref_pixel_green_1[7:0] green channel colour value at position 1
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.10.3.4 Phase distortion measurement
SAA6713AH
This phase distortion value could also be used for the frequency adjustment by sweeping the input frequency around the assumed target frequency. When auto-adjustment is in phase distortion mode, a signature is calculated for each frame. Changes inside the input stream can be detected by reading the signature bits ref_pixel_blue_0, ref_pixel_red_1, ref_pixel_green_1 and ref_pixel_blue_1. For still pictures, the signature does not change.
To help adjusting the phase for the ADCs, the SAA6713AH has a built-in phase distortion measurement which is calculating a 30-bit indicator value of a defined area of the video signal (see Table 35). The area for phase distortion measurements may contain active video or blanking. The area is defined by applying the upper left and lower right corner of the area to ref_col_0, ref_row_0 and ref_col_1, ref_row_1 respectively. Assuming a stable input picture with different pixel values inside the measurement window, the phase adjustment can be done by shifting the ADC phases and reading out the phase distortion indicator value of bits eval_row_0 and eval_col_0 for the maximum distortion value and eval_row_1 and eval_col_1 for the minimum distortion value. The best sampling phase corresponds to the highest value of the phase distortion indicator. Table 35 Mode 11 (phase distortion measurement) BIT Input values aa_submode[1:0] aa_cycles[1:0] not used measurement interval 00: 1 frame 01: 4 frames 10: 8 frames 11: 16 frames ref_col_0[10:0] ref_row_0[11:0] ref_col_1[10:0] ref_row_1[11:0] Output values eval_col_0[15:0] eval_row_0[15:0] eval_col_1[15:0] eval_row_1[15:0] ref_pixel_blue_0[5:0] ref_pixel_red_1[7:0] ref_pixel_blue_1[7:0] maximum of distortion[15:0] maximum of distortion[29:16] minimum of distortion[15:0] minimum of distortion[29:16] signature[29:24] signature[23:16] signature[7:0]
DESCRIPTION
measurement area upper left corner column measurement area upper left corner row measurement area lower right corner column measurement area lower right corner row
ref_pixel_green_1[7:0] signature[15:8]
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.10.3.5 How to use auto-adjustment
Example: from SXGA to XGA. 1024 Horizontal: ------------- x 64 = 51.20 1280
SAA6713AH
Table 36 Auto-adjustment steps STEP 1 2 3 4 7.11 ACTION program position values according to mode program mode, submode and cycle values to start auto-adjustment wait until interrupt appears read the according values Decoupling FIFO
This means dsc_h_incr = 51 and dsc_h_incr_corr = 20. 768 Vertical: ------------- x 64 = 48.00 1024 This means dsc_v_incr = 48 and dsc_v_incr_corr = 00. 7.12.2 UPSCALING
The decoupling FIFO allows an output line generation independent of the input line timing. The FIFO holds 1280 pixels, and either buffers incoming data when the vertical upscaling does not require any or holds back a line to be able to provide a continuous data stream in case of vertical downscaling. The FIFO output is locked after every line if line_lock is set to logic 1; otherwise after every frame and only released if the FIFO level exceeds the threshold level, given by fifo_threshold in units of 8 pixels. 7.12 Scaling
The upscaling engine is used for enlarging the incoming video frames. The magnification can be programmed individually for horizontal and vertical scaling. The maximum scaling factor for both directions is 64. The implemented filter algorithm uses interpolation with pixel enhancement, based on a free programmable transition function. Therefore, it is possible to define the transition between two calculated pixels to obtain different sharpness characteristics. This transition function must be defined in the 48 x 8 bits look-up table, with a number ranging from 0 to 64. Different functions can be programmed for horizontal and vertical scaling. The upscaler must be activated by usc_en. To set up the zoom factor, the scaling increments v_scale_incr, v_scale_corr, h_scale_incr and h_scale_corr must be programmed. number_of_output_pixels incr = ------------------------------------------------------------------ x 64 = xx.yy number_of_input_pixels Where xx is equivalent to v_scale_incr or h_scale_incr and yy is the fraction of the result in 1100. This is the value for programming the increment correction values v_scale_corr and h_scale_corr. Example: from XGA to SXGA. 1280 Horizontal: ------------- x 64 = 80.00 1024 This means h_scale_incr = 80 and h_scale_corr = 00. 1024 Vertical: ------------- x 64 = 85.33 768 This means v_scale_incr = 85 and v_scale_corr = 33. Remark: The last digit must be rounded up: 85.33 results in 1023.96 lines, but the upscaler will display only 1023 lines.
The SAA6713AH features separate scaling engines for upscaling and downscaling, for both horizontal and vertical processing. Two separate scaling units are implemented to perform upscaling and downscaling. 7.12.1 DOWNSCALING
The downscaling engine is used for reducing the incoming RGB data stream, i.e. for displaying high resolution input frames on panels with a smaller resolution. The scaling ratio can be programmed independently for both horizontal and vertical downscaling units. The algorithm uses pixel accumulation, achieving a minimum scaling factor of 164. If the downscaler is used, it must be enabled by setting dsc_en to logic 1. Setting-up the desired downscaling ratios is achieved by programming the scaling increments dsc_v_incr, dsc_v_incr_corr, dsc_h_incr and dsc_h_incr_corr. This must be done for both vertical and horizontal scaling. number_of_output_pixels incr = ------------------------------------------------------------------ x 64 = xx.yy number_of_input_pixels Where xx is equivalent to dsc_v_incr or dsc_h_incr and yy is the fraction of the result in 1100. This is the value for programming the increment correction values dsc_v_incr_corr and dsc_h_incr_corr. 2004 Apr 05 58
Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.12.3 HORIZONTAL FLIPPING
SAA6713AH
In Fig.17 an example of an 11 x 5 character window is shown that uses a total number of 55 elements. It should be noted that the parameters OSDT_WX and OSDT_WY are given in CHARACTER units, whether the offset of the window is given in PIXEL units. The real size of the OSD text window depends on the actual defined font resolution (OSDT_FR_X and OSDT_FR_Y), the actual zoom factor (zoom[1:0] value of 1, 2, 3 or 4 in register OSDT_CTRL0) and the rotate flag (rotate_right in register OSDT_CTRL0). So, the overall size of the OSD text in pixel is derived by calculating OSDT_WX x ZOOM x OSDT_FR_X respectively OSDT_WY x ZOOM x OSDT_FR_Y. In addition to this nominal window size, the optional window shadow feature (bit window_shadow) will extend the active OSD text area by the defined width and height (OSDT_WSHAD) multiplied with the actual zoom factor. Keep in mind that during rotation of the OSD, the core OSD text height and width will be visible exchanged, but the anchor position and the window shadow will not be seen (see Fig.18). From the application (software) point of view, the OSD programming does not change no matter if horizontal, vertical or flip flags are used or not. Only the display position registers (anchor) OSDT_PX and OSDT_PY must be chosen in a way that the now transposed OSD text window fits still in the picture. All matrix and font based accesses are automatically transposed, not even the index of the elements (cursor) has to be considered.
The SAA6713AH provides the possibility to flip horizontally the incoming picture. As flipping needs a line memory, both the downscaler and the upscaler have a flip programming register. When using the downscaler flip mode (flip_h = 1), no vertical downscaling can be performed. This is to be used when upscaling and flipping have to be programmed. In case downscaling and flipping shall be performed, flipping has to be done inside the upscaler by setting usc_h_flip to logic 1. 7.13 On screen display
The on screen display consists of three different and independent parts: OSD text, OSD bitmap and OSD pointer, where the OSD text is used as the `main' OSD part to build an application specific On Screen Menu (OSM). The bitmap part of the OSD is intended to be used for company logo or can be used as the backdrop of an OSM with up to 16 individual colours. As an addition for the graphical user interface in the OSM, the OSD pointer part allows a hardware cursor that is overlaid over picture data and the other OSD data. Its intention is to be used as a mouse pointer for selecting and modifying OSM items. Each of the three OSDs can be zoomed independently with pixel repetition by the factors 1, 2, 3 and 4 and can be rotated by 90 degrees clockwise, horizontally and vertically mirrored, if desired. All colour information used by the three OSD parts are organized in global colour tables (palettes) which define a certain colour each with 24-bit RGB data. These colour and palette registers are located at register page 9 (OSD colours). 7.13.1 OSD TEXT
The OSD text is a character based approach and consists of a window definition RAM, a font definition RAM and a font definition ROM. The window definition RAM gives the information about the data that is going to be displayed. It is organized as a character-based matrix that is free definable in terms of width and height (registers OSDT_WX and OSDT_WY) as long as the resulting number of elements does not exceed the maximum number of 1024 elements. Each element of this window matrix can directly accessed using the cursor registers OSDT_CURX and OSDT_CURY. The display position where the OSD text window is displayed in the picture, can be freely defined via the registers OSDT_PX and OSDT_PY.
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
OSDT_FR_X x zoom OSDT_PX 0,0 picture
OSDT_PY
0 11 OSDT_FR_Y x zoom
1 12
2 13
3 14
4 15
5 16
6
7
8
9
10
...
OSDT_WY (= 5)
...
52
53
54
MHC224
OSDT_WX (= 11) OSDT_CURX = 5 OSDT_CURY = 3
Fig.17 OSD window definition.
handbook, full pagewidth
OSDT_FR_Y x zoom OSDT_PX
OSDT_PY 10
picture
11 12 13 14 15 16
OSDT_FR_X x zoom
...
6
... 52 53 54
7
8
9
OSDT_WX (= 11)
0
1
2
3
4
5
MHC225
OSDT_CURX = 5 OSDT_CURY = 3
OSDT_WY (= 5)
Fig.18 OSD window horizontal, vertical, flip, rotate.
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
To allow easy access to the window definition when writing data to the OSD text, the cursor will perform an auto-increment function to the next right element (or to a new line, if the line ends) each time an element is written to the RAM which is allowing an I2C-bus burst transmission to define the window contents. The actual cursor values can be read back at any time. Each element of the OSD text window consist of 23 bits. They represent the property of an OSD text character. The elements are accessible via the OSDT_PROP2, OSDT_PROP1 and OSDT_PROP0 registers (see Table 37). All information encoded with these OSDT_PROP registers is valid for one character only, so the look of an OSD text can be changed mainly on a character base. The colour definition elements bg_colour[2:0] and fg_colour[2:0]/palette[2:0] are not defining a colour directly but are assigning a value from the Table 37 OSD property registers REGISTER OSDT_PROP2 OSDT_PROP1 OSDT_PROP0 D7 bg_colour[2:0] charcode[7:0] D6 blink[1:0] D5 D4 shadow D3 bg_trans D2 fg_trans
SAA6713AH
global OSD colour tables which are defined within register page 9. For single colour characters, the user can select one of the eight possible foreground colours and one of eight possible background colours. For multicolour characters one out of eight possible colour palettes is chosen; each defining four colours (1 background and 3 foreground) to be used within this character. The information whether a character is a multicolour character or a single colour character is derived from the charcode and the value of sc_startcode (OSDT_SC_HI and OSDT_SC_LO) that defines the multi or single character mapping inside the font RAM.
D1 bg_alpha ROM
D0 fg_alpha charcode[8]
fg_colour[2:0]/palette[2:0]
Table 38 OSD property registers bit description BIT blink[1:0] defines the blink mode of the character 00: blinking is off 01: blinking of foreground only 10: character is inverse, no blinking 11: blinking by inversion of foreground and background colour shadow bg_trans fg_trans bg_alpha fg_alpha bg_colour[2:0] fg_colour[2:0]/ palette[2:0] ROM charcode[8:0] if set to logic 1, the character will be displayed with an 1 pixel horizontal and vertical shadow if set to logic 1, the background colour is displayed transparent if set to logic 1, the foreground colour is displayed transparent if set to logic 1, the background will not be displayed solid but alpha-blended with picture data using the global definable background alpha-blending factor (OSDT_BGA) if set to logic 1, the foreground will not be displayed solid but alpha-blended with picture data using the global definable foreground alpha-blending factor (OSDT_FGA) defines which of the 8 definable text background colours is used for this character shared programming bits; fg_colour defines which of the 8 text foreground colours is used for this character (only valid if charcode points to a single colour character) and palette defines used multicolour palette (only valid if charcode points to a multicolour character) if set to logic 1, the character is selected from ROM; if set to logic 0, then the character is selected from RAM indicates the desired character inside the font ROM/GEN or the font RAM DESCRIPTION
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
Different property register write modes can be selected, allowing to accelerate the I2C-bus programming of OSD windows with characters sharing the contents of one or more property registers. Parameter write_mode of register OSDT_MASK (see Table 39) controls which of the three property registers OSDT_PROP2 to OSDT_PROP0 have to be updated until the character information is internally written into the window RAM. The registers are activated by write_mode according to Table 41. Only once all activated registers have been updated via the I2C-bus, the character is written into the window RAM and the cursor position defined by OSDT_CURX and OSDT_CURY is advanced to the next window element. The information of an inactive property register is still included in the character definition, but the register does not have to be rewritten for every new character definition. Example 1: for a single-coloured ASCII character-based OSD, write_mode is set to `001' and property registers OSDT_PROP2 and OSDT_PROP1 have only to be defined initially, all window elements are then defined by consecutive writing of OSDT_PROP0. With every write operation to OSDT_PROP0 a new window element is defined. The I2C-bus burst access is also supported for the property registers specified by parameter write_mode as Table 39 OSDT_MASK register REGISTER D7 D6 D5 D4 fg_mask D3 D2
SAA6713AH
specified in Table 41. The active property register values of consecutive window elements can be transmitted in the I2C-bus burst mode without the requirement of repeating device addressing and the transmission of the subaddress for every character or property register. Example 2: for a multi-coloured OSD, write_mode is set to 6 to activate only OSDT_PROP1 and OSDT_PROP0. OSDT_PROP2 is set initially. The OSD can then be programmed with one I2C-bus write burst consisting of device addressing byte, the OSDT_PROP1 subaddress followed by OSDT_PROP1 value of first character, OSDT_PROP0 value of first character, OSDT_PROP1 value of second character, OSDT_PROP0 value of second character, OSDT_PROP1 value of third character etc. After each transmission of an OSDT_PROP0 value the character definition is transferred into the window RAM. The masking bits (see Table 40) are used as a data filter that specifies which parts of the complete OSDT_PROP word (23 bits) are written to the RAM and which are masked out. Each attribute will only be updated in the OSD text window RAM element if its mask bit is set to logic 1. If that is not the case, the window RAM will ignore this part of the OSDT_PROP register and will keep up its previously defined value for this part at the selected OSD text window element.
D1
D0
OSDT_MASK blink_mask shadow_mask bg_mask Table 40 OSDT_MASK register bit description BIT blink_mask shadow_mask bg_mask
code_mask write_mode[2:0]
DESCRIPTION 1: blink[1:0] property will be written according to actual OSDT_PROP2 settings 0: blink[1:0] property will not be modified 1: shadow property will be written according to actual OSDT_PROP2 settings 0: shadow property will not be modified 1: all background information will be written according to actual property settings (OSDT_PROP2: bg_trans, bg_alpha and OSDT_PROP1: bg_colour) 0: the background property will not be modified 1: all foreground information will be written according to actual property settings (OSDT_PROP2: fg_trans, fg_alpha and OSDT_PROP1: fg_colour) 0: the foreground property will not be modified 1: the charcode property will be written according to actual property settings (OSDT_PROP1: ROM, charcode[8] and OSDT_PROP0: charcode[7:0]) 0: the charcode property will not be modified write mode selection (see Table 41)
fg_mask
code_mask
write_mode[2:0]
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
Table 41 Write mode selection write_ mode[2] 0 0 0 0 1 1 1 1 write_ mode[1] 0 0 1 1 0 0 1 1 write_ mode[0] 0 1 0 1 0 1 0 1 - OSDT_PROP0 OSDT_PROP1 OSDT_PROP1 and OSDT_PROP0 OSDT_PROP2 OSDT_PROP2 and OSDT_PROP0 OSDT_PROP2 and OSDT_PROP1 OSDT_PROP2 to OSDT_PROP0 ACTIVE I2C-BUS REGISTERS - burst access to OSDT_PROP0 burst access to OSDT_PROP1
SAA6713AH
I2C-BUS SUBADDRESS AUTO-INCREMENT HANDLING
sequential access to OSDT_PROP1 OSDT_PROP0 OSDT_PROP1 etc. burst access to OSDT_PROP2 sequential access to OSDT_PROP2 OSDT_PROP0 OSDT_PROP2 etc. sequential access to OSDT_PROP2 OSDT_PROP1 OSDT_PROP2 etc. sequential access to OSDT_PROP2 OSDT_PROP1 OSDT_PROP0 OSDT_PROP2 etc. As described before: all definitions of the OSD window elements are just defining the property of a character and are pointing to a font definition by the charcode attribute. The real character contents are taken from either the font ROM/GEN part or the font RAM part of the OSD text indexed by that charcode. The font definition ROM/GEN is already providing a large amount of predefined fonts as illustrated in Fig.19.
The combination of the mask bits and the write_mode already provides a powerful way to speed any OSM drawings by minimizing the needed I2C-bus transmissions, but there is even more hardware support for defining an area inside the OSD text window which has the same element property for all elements within its boundaries. An area can be defined using the upper-left and bottom-right cursor coordinates inside the OSD text window matrix using the OSDT_FAULX, OSDT_FAULY, OSDT_FABRX and OSDT_FABRY registers. The execution of the writing is initiated by writing a logic 1 to areafill_start (register OSDT_CTRL0) and as before, the current value of the complete 23-bit OSDT_PROP word is written to each element of the defined area. Of course, the mask bits are still valid and can be used also during an areafill execution. So, this function can not only be used to overwrite and clear areas inside the OSM, it can also be used to highlight or blink certain areas in the OSM. It should be noted that it might be needed to set the write_mode to `000' if you want to change any of the OSDT_PROP settings previous to an areafill and assure that no write and cursor auto-increment is done accidentally.
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ndbook, full pagewidth
2004 Apr 05
0 00 01 02 03 04 05 06 07 1 2 3 4 5 6 7 8 9 A B C D E F
Philips Semiconductors
XGA analog input flat panel controller
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
11 12 13 14 15 16 17 18 19 1A generated 1B 1C 1D 1E 1F
64
08 09 0A 0B 0C 0D 0E 0F 10
MHC226
SAA6713AH
Product specification
Fig.19 ROM/GEN character codes.
Philips Semiconductors
Product specification
XGA analog input flat panel controller
The character codes from 000H to 15FH (see Table 42) are ROM defined characters with the natural resolution of 12 x 18 pixels, so the font resolution defined via OSDT_FR_X and OSDT_FR_Y should be set to 12 and 18 to achieve optimal viewing results. If the actual font resolution is defined greater than 12 x 18, all ROM characters will be centred automatically inside the programmed font size; if it is less than 12 x 18 the characters will be cropped. This handling allows ROM and RAM characters to be displayed together in one OSD, even if the RAM font size does not fit the ROM size of 12 x 18 pixels. Looking at Fig.19 it is easily seen that the ROM is using six different subareas for the charcode. The addresses from 160H to 1F6H are mapped to the internal character generators (GEN). Despite the real ROM definitions these characters do not have a native resolution instead they will always be displayed in the actual defined font resolution (OSDT_FR_X and OSDT_FR_Y) itself. While the border characters of the font GEN are kept fixed and just adapted to the used font size, the slider parts are generated based on its parameters OSDT_SLP1 and OSDT_SLP0 (see Table 43). Table 43 Slider property registers REGISTER OSDT_SLP0 Table 44 Slider property registers bit description BIT slider_offset[3:0] slider_border[3:0] slider_gap[3:0] slider_style thickness of slider border in pixel gap between slider border and slider core in pixel DESCRIPTION distance from the character border to the generated slider in pixel D7 D6 D5 D4 D3 slider_offset[3:0] slider_style slider_gap[3:0] D2 Table 42 ROM mapping ADDRESS (HEX) 000 to 01F 020 to 02F 030 to 04F 050 to 05F 060 to 112 113 to 15F 160 to 1D1 1D1 to 1F6
SAA6713AH
CONTENTS multicolour, dual character symbols multicolour, single character symbols single colour, dual character symbols single colour, single character symbols single colour, ANSI like character set with ASCII mapping (ASCII code + 60H) single colour, basic Japanese font set single colour, border and line characters multicolour generated slider parts
D1
D0
OSDT_SLP1 slider_border[3:0]
0: fill; middle slider parts are solidly filled from left to right and from bottom to top 1: peak; middle slider parts are created with a single marker at reference position
2004 Apr 05
65
Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
OSDT_FR_X offset
border gap OSDT_FR_Y
S
M fg = 16
M fg = 16
M fg = 7
M fg = 0
E colour 0 (BG) colour 1 (FG) colour 2 (FG)
MHC227
colour 3 (FG)
Fig.20 Multicolour slider generation.
When putting together a slider with multiple characters (see Fig.20), a slider always consists of three basic parts: a start part (S), a middle part (M) with different fill grades (fg) and an ending part (E). The start part is always located at address 1D2H (horizontal) respectively 1F6H (vertical) and the end part is always located at 1E3H respectively 1E4H. The characters in between the start and the end character correspond to different fill grades of the middle part that are needed to give a subcharacter precision in a custom slider. In this system the middle part uses a natural resolution of 16 pixel per character which is resulting in 17 different characters from empty to full. If the display size is different from the natural resolution, either some fill grades will be skipped or some fill grades will be doubled within the 17 characters that are reserved to represent the middle parts. Anyhow mathematically, it is always correct to use the slider resolution of 16 to calculate the fill grade of the last partly filled slider part and use this value directly to index to the correct middle part. Using this approach results in an overall slider resolution equal to the number of used middle characters multiplied by 16 to graphically display any values within an OSM either with a fill bar or a single marker. To achieve more flexibility in the OSD look, 4 kbyte of user definable RAM can be used in addition to the ROM/GEN
characters. This font definition RAM can contain a downloadable mixed multicolour or single colour font which is in terms of character size freely programmable via OSDT_FR_X and OSDT_FR_Y registers but has to be between 8 x 8 and 32 x 32 pixels. This font resolution is valid for all characters inside the RAM, no matter if they are defined in single colour or multicolour but a single colour pixel can be stored with one while a multicolour pixel occupies two bits inside the font RAM. For single colour characters a pixel of value `0' will be displayed as background and a pixel data of value `1' will be displayed as foreground according to the defined colour values in the OSDT_PROP registers and the OSD colour definitions on register page 9. For multicolour characters always two bits are taken for each pixel that directly map to the four colour value inside the selected multicolour palette which is also defined in register page 9 and is selected within OSDT_PROP. The font RAM (see Table 45) can store a maximum number of 512 8 x 8 single colour characters which corresponds to the 9-bit charcode in the OSDT_PROP registers. Using multicolour definitions that need two bits per pixel and/or larger font resolution reduces of course the number of possible characters to be stored in the font RAM.
2004 Apr 05
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
The multicolour font definitions have to start always from address 0 and the start of the single colour definitions is indicated by the configurable single colour start code (OSDT_SC register). This means all the characters with charcodes below the OSDT_SC value are treated as multicolour and all charcodes above this value are handled as single colour characters. To use only multicolour characters in the RAM font set this value must be set to an unreachable value. Due to the RAM size of 4 kbyte a multicolour 8 x 8 font with 2 bits per pixel can hold 256 characters as maximum so it is enough to set only bit 8 in OSDT_SC_HI register to logic 1. To use only single colour definitions set the complete OSDT_SC pointer simply to 000H. A character is stored in the font RAM using the OSDT_CC_HI, OSDT_CC_LO, OSDT_CMASK and OSDT_CDEF registers where OSDT_CC gives the charcode of the character to be defined and OSDT_CDEF and OSDT_CMASK are used for the data bits and the according mask using 8 bits at a time. Table 45 Examples of possible font RAM configurations STORABLE CHARACTERS FONT SIZE COLOUR 8x8 single colour only multicolour only mixed example 12 x 16 single colour only multicolour only mixed example 12 x 18 single colour only multicolour only mixed example 9 x 13 single colour only multicolour only mixed example 24 x 24 single colour only multicolour only mixed example 32 x 32 single colour only multicolour only mixed example 512 256
SAA6713AH
The data format written to OSDT_CDEF has to be MSB aligned representing the following pixel of the character with the pixel sequence processed from top to bottom and left to right. As mentioned before, a single colour pixel is represented with one bit while a multicolour pixel needs two bits to be described. So each definition of a character will need multiple writes to OSDT_CDEF (8 bits at a time) until the whole character is completed. The total number of bytes to be transmitted is depending on the defined font size and if the character uses a single or multicolour definition.
MAXIMUM NUMBER
256 single colour and 128 multicolour 170 85 100 single colour and 35 multicolour 151 75 121 single colour and 15 multicolour 280 140 200 single colour and 40 multicolour 56 28 40 single colour and 8 multicolour 32 16 24 single colour and 4 multicolour
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Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
BYTE 1 BYTE 2 BYTE 3
BYTE 1 BYTE 3
BYTE 2 BYTE 4 ...
OSDT_FR_Y (= 11)
BYTE 4
OSDT_FR_X (= 9)
OSDT_FR_Y (= 11)
...
OSDT_FR_X (= 9)
MHC228
a. Single colour definition sequence (needs 9 x 11 = 99 bits 13 bytes).
b. Multicolour definition sequence (needs 9 x 11 x 2 = 198 bits 25 bytes).
Fig.21 Data format of the OSD font RAM.
It should be noted that the characters are not stored byte-aligned in the internal RAM due to the programmable font sizes (see Fig.21). Due to this, a bit-exact address is internally needed that points to the first bit of a character inside an 8-bit data word. This internal character base address is calculated new, each time data is written to either the OSDT_CC_HI or OSDT_CC_LO register and is incremented by 8 bits on each write to OSDT_CDEF. During each write the actual value of the OSDT_CMASK register is used. So for an 8 x 8 single colour character to be defined, simply set OSDT_CC to the desired charcode, set all bits of OSDT_MASK to logic 1 and write 8 times to OSDT_CDEF to define the complete character. For a 9 x 9 single colour character (needs 81 bits) you have to do 11 writes to OSDT_CDEF, even if only the MSB of the 11th transmission is used and the remaining 7 bits stay unused. One could now either use masked writing to mask those bits 6 to 0 out (so the following character definition is not touched) or immediately continue with the definition of the next character and simply connect the next character data to bit 6 down to bit 0. Because the IC cannot determine which functionality is desired, the user can select this by setting the OSDT_CC register. If an automatic masking at the end of each character is desired, the flag single_char_def (OSDT_CC_HI[7]) can be set to logic 1. This means that before the next character definition the 2004 Apr 05 68
desired charcode must be written again, because the internal bit address does not longer match with the following character base address. Otherwise, if this bit is kept to logic 0, the internal bit address is continued over character boundaries allowing multiple bit-packed character transmission in a sequence. Only the last definition might need a manual masked writing in case of an address space overflow or if any needed data is present at higher charcodes. To reduce the programming time for the font RAM, an auto-increment function is used internally so that an I2C-bus burst transmission can be used to transmit as many 8-bit data words as needed, even configuring all characters in one continuous burst. To allow this, the SAA6713AH register auto-increment is re-addressing OSDT_CDEF after each write to OSDT_CDEF. Any changes to the OSD text RAM definitions can also be made while the OSD is displayed. So the usable character set is only limited by the size of the external microcontrollers ROM. Just keep in mind that due to internal address calculation, the font size (OSDT_FR_X and OSDT_FR_Y) and the single colour start code (OSDT_SC_LO and OSDT_SC_HI) must be defined prior to any font definition, in order that the character data will not look disturbed.
Philips Semiconductors
Product specification
XGA analog input flat panel controller
7.13.2 OSD BITMAP
SAA6713AH
possibility to define either the foreground or the background from transparent to solid. The display colours are again defined on a separate osd_bitmap palette inside the osd_colour definition page 9 so each pixel can use one of the defined 16 colours where bitmap colour 0 is always treated as background. The OSD bitmap uses an internal memory of 4 kbyte RAM in which the graphic pixels are stored (see Table 46). It can be parametrized freely in width (OSDB_SX), height (OSDB_SY) and colour depth (OSDB_CTRL1[6:5], bits per pixel) with the restriction that the needed memory size still fits into the 4 kbyte memory address space.
The OSD bitmap part can be used for displaying pixel based multicolour graphics along with the regular text based OSM (see Fig.22). Its display position can be defined anywhere in the picture (OSDB_PX and OSDB_PY) and like the OSD text it can be zoomed, flipped and rotated according to the settings within its control register OSDB_CTRL0. It is allowed to overlap with a displayed OSD text window if desired. In this event the bitmap_behind flag (OSDB_CTRL0[6]) defines whether the bitmap part appears on top or behind the OSD text information. Two separate alpha-blending values (bg_alpha and fg_alpha) define a blending value for the OSD bitmap and separate transparent flags provide the
handbook, full pagewidth
OSDB_PX picture
OSDB_PY
OSDB_SY (= 11)
MHC229
OSDB_SX (= 12)
Fig.22 OSD bitmap structure.
Table 46 Bitmap RAM configurations; note 1 BPP CODE 00 01 1X Note 1. X = don't care. USED BITS PER PIXEL 1 2 4 USED COLOURS 2 4 16 DISPLAYABLE PIXELS 32768 16384 8192 EXAMPLE WINDOW SIZES (NOT ZOOMED) 256 x 128; 181 x 181 256 x 64; 128 x 128 256 x 32; 90 x 90
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Product specification
XGA analog input flat panel controller
The access to the graphic memory is based on a masked writing with pixel exact addressing (see Fig.23) via the write cursor (OSDB_CX, OSDB_CY) always configuring 8 bits at a time (OSDB_DEF) with data being processed from left to right and top to bottom. Using the 8 corresponding mask bits (OSDB_MASK) any pixel within the OSD bitmap can directly be accessed and redefined without changing neighbouring pixel also during display time allowing software guided animations for fancy start-up screens. Both the OSDB_DEF and OSDB_MASK are always MSB aligned which means that bit 7 will be written to the pixel address that is referenced by the OSD bitmap cursor (OSDB_CX, OSDB_CY). Depending on the selected bitmap size and the number of colours to be used this pixel address will probable not be byte aligned but the user does not have to take care of any internal alignments. The next 8 bits that are written to OSDB_DEF will be written bit wise starting with the MSB from the given cursor location.
SAA6713AH
In order to speed up the OSD bitmap definitions the internal RAM address is incremented by 8 bits always when a write to OSDB_DEF happened. Together with a stop of the SAA6713AH register auto-increment at this register, this allows a fast burst configuration of multiple pixel up to a complete OSD bitmap definition setting the cursor to (0,0), the mask to FFH and writing all needed data bytes in a single burst. The number of needed byte transmissions is derived by multiplying the total number of pixels to be configured with the used bits per pixel and dividing this result by 8 bits. When overwriting parts of the bitmap image the user must handle the OSDB_MASK flags for the remaining bits that shall not overwrite any data by himself.
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byte 2 byte 4
byte 1 byte 3
...
3
byte 4
byte 1 ...
byte 2
byte
b1 b2
b3
b4
1 bit per pixel 2 colour definition (bits per pixel code = 00)
2 bits per pixel 4 colour definition (bits per pixel code = 01)
4 bits per pixel 16 colour definition (bits per pixel code = 1X)
MHC230
start position of configuration: OSDB_CX = 4, OSDB_CY = 6 OSD bitmap defined with OSDB_SX = 14 and OSDB_SY = 19
Fig.23 Data format of the OSD bitmap RAM.
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7.13.3 OSD POINTER
SAA6713AH
The definition of the OSD pointer RAM is similar to the definitions of the OSD bitmap RAM. The data is written MSB-aligned to the OSDP_DEF register using 2 bits per pixel. It is written starting from the pixel-exact coordinates given with the OSD pointer cursor (OSDP_CX and OSDP_CY). Instead of using a masked writing the definition width giving the number of pixels that are used from the OSDP_DEF register and written from the given start position can be set via the OSDP_DW register. As in the preceding OSD units also the OSD pointer uses an auto-increment always setting the cursor to the following definition position on each write to OSDP_DEF where the increment is depending on the actual used defwidth. Together with stopped SAA6713AH register auto-increment at OSDP_DEF, this allows a fast burst definition mode that needs 256 I2C-bus byte transmissions to define a complete pointer buffer (see Table 47).
The OSD pointer icon is a four colour 32 x 32 pixel structure and is intended to be used as a cursor on top of an OSM (see Fig.24). It is very much alike the OSD bitmap part allowing individual positioning (OSDP_PX_HI, OSDP_PX_LO, OSDP_PY_HI and OSDP_PY_LO), zooming, flipping and rotating (OSDP_CTRL0) but will always be displayed on top of any OSD text or OSD bitmap window. It is fixed in its resolution and always uses 2 bits per pixel allowing 4 possible colours. Those colours are again definable via a palette in the OSD colour settings (register page 9) where colour 0 is always treated as background colour. The foreground and the background colours can be displayed from solid to almost transparent with an individual alpha-blending factor (OSDP_FGA and OSDP_BGA) or fully transparent using fg_trans and bg_trans flags inside the OSDP_CTRL1 register. For animation purpose of the icon, it is double buffered and able to generate a frame based switching interrupt. The buffer to be displayed can either be selected manually via the buffer_sel flag (OSDP_CTRL0[6]) or can be switched automatically on each generated interrupt (OSDP_CTRL0[7]). During the display of one buffer all writes are redirected to the inactive buffer. The period of the animation interrupt can be adjusted with the OSDP_AD register that defines the number of frames between two interrupts. The interrupt generation itself can be enabled with the anim_int_en flag (OSDP_CTRL1[5]).
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Product specification
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SAA6713AH
handbook, full pagewidth
32 pixel ...
32 pixel
MHC231
single pixel definition with OSDP_CX = 20, OSDP_CY = 21 and OSDP_DW = 00 burst definition data bytes with OSDP_CX = 0, OSDP_CY = 0 and OSDP_DW = 11
Fig.24 Data format of the OSD pointer.
Table 47 OSD pointer definition width defwidth[1:0] 00 01 10 11 PIXELS TO BE DEFINED 1 2 3 4 USED BITS FROM OSDP_DEF 7 and 6 7 to 4 7 to 2 7 to 0 NEEDED TRANSMISSIONS FOR A COMPLETE BUFFER 1024 512 342 256
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7.13.4 HOW TO USE OSD
SAA6713AH
7.13.4.5 How to use pointer animation
7.13.4.1
How to create a simple single colour OSD text
1. Set the OSDP cursor to 0,0 and OSDP_DW to `11'. 2. Define the desired animation speed via OSDP_AD, enable the pointer animation interrupt and enable automatic switching. 3. On each interrupt send a 256 byte burst containing the next picture of the animations to OSDP_DEF. It should be noted that this must be finished before the next interrupt arrives.
1. Define the desired font size you want to use (OSDT_FR_X and OSDT_FR_Y). 2. If RAM font is needed: set OSDT_SC to logic 0, set OSDT_CC_HI to logic 0, set OSDT_MASK to FFH and define as many characters as wished by sending the needed number of data bytes to OSDT_CDEF preferable using an I2C-bus burst transmission. 3. Define the OSD text window size (OSDT_WX and OSDT_WY), set the cursor to OSDT_CURX = 0 and OSDT_CURY = 0. 4. Set OSDT_MASK to FFH forcing all data to be written, all data to be configured. 5. Define the window content by all three OSDT_PROP registers defining the attributes, colours and charcodes. Use an I2C-bus burst transmission to speed up the programming. 6. Set the desired position and orientation and enable the OSD text with text_on flag that resides in OSDT_CTRL0.
7.13.4.6
Remarks on the configuration of the OSD
The three OSD parts can be used independently. If all three parts are turned off, the whole OSD module will be bypassed and clocked down to reduce the power consumption. Most of the registers of the OSD can be reprogrammed during processing except some needed definition parameters e.g. the resolution and sizes that need to be defined at start-up in order to guarantee correct address calculations. Before defining the font RAM a valid font size, a valid charcode and a valid sc_startcode must be defined. A burst definition with new address calculations to the OSD font RAM is only possible either in the multicolour or the single colour area of the memory. So if both areas are to be defined you should define the RAM in two bursts, one for the multicolour and one for the single colour characters. With some effort it is of course possible to write down a user-packed byte burst to speed up the software init that includes all the multicolour and single colour information and create the corresponding font size afterwards. If something is not displayed as expected, you should carefully check the write mode. Data will only be accepted when all of the corresponding OSDT_PROP registers are written. To speed up clears or highlighting, the areafill function should be used. By setting the areafill_start bit, an area of the text window within the defined area boundaries is overwritten using the actual settings of OSDT_PROP[2:0] registers and the OSDT_MASK register.
7.13.4.2
How to make changes to a displayed OSD text
1. Just set the cursor to the desired position and set the desired mask and write mode. 2. Overwrite the character by writing the new OSDT_PROP registers defining new attributes, colours or charcodes.
7.13.4.3
How to create fade-in and fade-out effects
1. Define the desired elements of the OSD text window to be alpha-blended. 2. Modify the values of OSDT_BGA every few frames in the desired direction by a certain value.
7.13.4.4
How to display a company logo
1. Define the OSD bitmap part in the needed resolution and the available colour depth. 2. Set the OSDB cursor to 0,0; set OSDB_MASK to FFH. 3. Send all needed bytes with the correct used bits per pixel to OSDB_DEF register, preferable in a burst sequence and turn the OSD bitmap on.
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The text shadow is generated over the whole OSD and just displayed in the enabled characters. So it is not character bound. This means that a neighbouring `non-shadowed' character can throw part of its shadow in the shadow allowed character. Also the text shadow is only able to work correct if the whole OSD is inside the picture boundaries and will be turned off automatically if this is not the case. The generated shadow is treated as background, so the shadow is alpha-blended with the background alpha-blending factor, but the shadow is never displayed transparent. During any configuration with the cursors in either the OSD window or one of the pixel addresses be aware that the cursor will `wrap around' if the calculated address exceeds the physical memory address space. 7.14 Colour look-up table
SAA6713AH
horizontal blanking, which slows down programming speed. Colour look-up is enabled by setting cc_on to logic 1; otherwise the colour look-up tables are in bypass mode and the image values consist of the original value in the upper eight bits and both LSBs are set to logic 0. Programming of the look-up tables is possible in bypass mode or during data processing. 7.15 Dithering unit
The colour look-up table unit (or gamma correction unit) performs gamma correction and colour component brightness and contrast adjustment. Each 8-bit RGB component value is mapped to a programmable 10-bit value by using it as an index for a look-up table that returns the corresponding image value. The colour components are processed by three independent tables. The output value for each index value is programmed by writing the 8-bit index to register CL_INDEX and then programming registers CL_VALUE_HI (02H) and CL_VALUE_LO (03H) with the 10-bit image value. Each of the three look-up tables is individually activated for programming by setting red_prog, geen_prog or blue_prog respectively to logic 1. The activated tables are updated with the new value pair when the lower byte of CL_VALUE_LO (03H) was written. To support quick programming of consecutive values, the index value is incremented after every completed write, so CL_INDEX does not have to be reprogrammed for every data pair. Also the I2C-bus subaddress auto-increment is overridden when writing to CL_VALUE_LO. Instead the subaddress for the next write is determined according to register CL_CTRL. If quick_prog is set logic 0 the subaddress for the next write is set back to 02H (CL_VALUE_HI); otherwise it remains 03H (CL_VALUE_LO), which allows sequential writes of the lower byte only. As the look-up tables can only be either written or read at the same time, during write operations with activated colour look-up the tables are bypassed. To avoid any influence on the output picture, write_hsynced can be set to logic 1 to update the look-up tables only during
The dither unit improves the visual quality of displays with only 6-bit or 8-bit physical colour resolution to a virtual colour depth of 10 bits. This is achieved through temporal variation of the physically possible colour values. To reduce artefacts of the temporal variation neighbouring pixels follow different sequences of variation. The dithering unit registers are mapped to page 10, registers 80H to 83H. Dithering is switched on if dither_bypass is set to logic 0; otherwise the dithering unit is bypassed. The colour depth of the target display is selected by dither_out_bits. For an 8-bit panel dither_out_bits is set to logic 1; for a 6-bit panel the programming bit is set to logic 0. Bits dither_idx_ofs_reg[2:0] give a choice of variation sequences (see Table 48). Best quality is expected for most displays with the setting random. Table 48 Dithering sequences; note 1 dither_idx_ofs_reg[2:0] 000 001 010 011 1XX Note 1. X = don't care. Additionally, the unit adds LSB noise to the 10-bit colour values from the colour look-up table, when enabled by dither_add_noise = 1, which improves visual display quality of certain 10-bit displays (e.g. plasma displays). The noise includes only one LSB if dither_noise_mag is set to logic 0; otherwise two LSBs. Configuration parameters dither_colmap, dither_rand_mono and dither_rand_mode are for test purposes and should be left in their reset values. SEQUENCE constant zero 2 x 2 Bayer 4 x 4 Bayer 5 x 5 special random
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Product specification
XGA analog input flat panel controller
7.16 Output interface
SAA6713AH
The active frame is divided into border and picture area. The picture area includes the data from the input stream. The border area is around the picture area. If no border is needed, the register values of picture and active area have to be equal. The active frame can be put anywhere inside the main frame except in the first row or in the first column of the main frame. The geometric values for the frames/areas depend on the display and the timing. If the picture values are not correct data may be lost or missing data will be replaced by border colour. The serial output begins in the upper left corner of the main frame in row 1 and column 1. The active frame starts in row active_start_y and in column active_start_x (point a in Fig.25). Values 0 are not allowed and the active frame or the picture area cannot start in column one. The picture area has to be contained in the active frame, at maximum it may be identical to the active frame.
The Output Interface (OIF) provides picture data and command signals to the display. Programming the output interface, the output frame geometry can be defined. As most displays require continuous data stream during one frame or line, it is possible to define wait points. There are different possibilities how to map the RGB data to the output ports PA to PF. The SAA6713AH does not have particular output ports for panel signals VSYNC, HSYNC or DE. Instead, there are in total 10 Configurable Signal Generator (CSG) outputs which are driven by free programmable CSGs. All output interface programming registers are mapped to the I2C-bus configuration register page 11. 7.16.1 DEFINITION OF THE OUTPUT FRAME GEOMETRY
The total output frame area (main frame) is defined by blank_line_length and last_line (registers OI_FX and OI_FY). It consists of the visible data (active frame) and the invisible data (blanking); see Fig.25 and Table 49.
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1,1 a border area b
picture area
c active frame d last_line main frame
MHC232
e blank_line_length
Fig.25 Output frame set-up.
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Table 49 Programmable geometric values POINT a b c d e HORIZONTAL active_start_x (OI_ASX) picture_start_x (OI_PSX) picture_end_x (OI_PEX) active_end_x (OI_AEX) blank_line_length (OI_FX)
SAA6713AH
VERTICAL active_start_y (OI_ASY) picture_start_y (OI_PSY) picture_end_y (OI_PEY) active_end_y (OI_AEY) last_line (OI_FY)
To make timing adaption of output to input frame easier, each area has its own line length, i.e. the blanking behind the border area can be freely adjusted. As some panels are sensitive to different line lengths, they should differ as little as possible. All line length values have to be greater or equal to active_end_x. Parameter active_end_x must be greater or equal to picture_end_x. The according programming registers are listed in Table 50. Border and blanking colour are freely programmable as described in Table 51. Table 50 Line length values AREA Blanking Border Picture Table 51 Border and blanking colour AREA Blanking Border REGISTER OI_BLC_R, OI_BLC_G and OI_BLC_B OI_BOC_R, OI_BOC_G and OI_BOC_B LINE LENGTH blank_line_length (OI_FX) active_line_length (OI_ALX) picture_line_length (OI_PX)
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7.16.2 WAIT MODES
SAA6713AH
new picture data is available. If fieldwise wait mode is programmed, the output only stops at the wait_column of the first line of the picture area. The wait_column must be located in front of the active area (see Fig.26). Additionally, there is a free-running mode without any wait point. The wait modes are programmed in register OI_WM according to Table 52.
It is not necessary to match the output timing exactly to the input timing. The output timing can be a little faster. In this event it may happen that no valid data is available at the OIF. As the output stream to the panel should not be interrupted during the output of a frame or line, a line wise and a frame wise wait mode is available. The wait_column (register OI_WX) has to be programmed. During output of lines inside the picture area, the output stream stops at this defined wait_column and waits until
handbook, full pagewidth
1,1
first row continuous picture data
waiting possible
picture area
active frame last_line main frame blank_line_length wait_column
MHC233
Fig.26 Wait column.
Table 52 Wait modes wait_mode[1:0] 11 10 01 00 row stop one stop waiting in each row of picture area waiting in first row of picture area once each frame MODE free-running no waiting ACTION
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XGA analog input flat panel controller
7.16.3 DATA TO OUTPUT MAPPING
SAA6713AH
Registers OI_B0R, OI_B0G, OI_B0B, OI_B1R, OI_B1G and OI_B1B have to be programmed according to Table 53.
Each colour of each pixel is handled separately. In double pixel mode there are 6 bytes (red, green and blue of pixel 0 and pixel 1 from which pixel 0 arrives first). In single pixel mode there are 3 bytes (red, green and blue of pixel 0). Each of the six output ports (see Fig.27) can be connected to each colour and can be inverted, swapped and aligned to the MSB (sensible to drive 6-bit panels).
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R0 MSB BLANK GENERATION, BORDER GENERATION, TRANSITION MINIMIZING G0 B0 R1 2 bits G1 B1 8 bits each 6 bits
PA PB PC PD PE PF
MHC234
48 bits
LSB
Fig.27 Data to output mapping schema.
Table 53 Data to output mapping; note 1 BIT MSB_align swap inv port_x_conf[2:0] FUNCTION alignment swapping inversion allocation ACTION If this bit is set to logic 1, then the lower 6 bits are aligned to MSB. If this bit is set to logic 1, then swap [7:0] to [0:7]; LSB becomes MSB. If this bit is set to logic 1, then bit wise inversion of the colour component. Output port Px gets data byte with 6 bytes in double pixel mode or 3 bytes in single pixel mode (for x = A to F): 11X: 0R 101: 0G 100: 0B 01X: 1R 001: 1G 000: 1B Note 1. X = don't care.
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7.16.4 CONFIGURABLE SIGNAL GENERATORS
SAA6713AH
The operation window upper left corner (a) is defined by the OI_GxSX and OI_GxSY registers and the lower right corner (b) is described by the OI_GxEX and OI_GxEY registers (x out of 0 to 9). The action is defined by programming the configuration register OI_GxC. The corners (a and b) of the operation window are the action points. In each action point the output signal is modified as described in the configuration register. At the first action point (a) the output will be set or toggled. At the second action point the output signal will be reset or toggled again. Example: In order to define a DE signal, the CSG window is set to the active area. Bit frame or bit line of the concerned CSG control register is set to line mode and the CSG signal is set to logic 1 at point 1 and set to logic 0 at point 2 (see Figs 29 and 30). Important programming hint: The horizontal start values (x-values) of the action points describe the offset from the beginning of the line. If you want to start e.g. CSG0 at (2,3) you have to program the values (1,3). If you want to stop the signal after (12,14) you have to program the values (12,14) so the signal changes its value at the end of position 12 (edge to position 13). An offset of 0 is not allowed. Avoid using the same column as wait column. There are 4 groups of CSGs. The CSGs of each group have some other additional features.
There are 10 configurable signal generators available. The functionality is particularly designed to drive displays directly without the use of a Timing Controller (TCON). For operation with hsync, vsync and data enable only three generators are needed. All CSGs have the same basic structure (see Fig.28). There are two programmable action points: the start point (a) and the end point (b). The start point describes the upper left corner of the operation window. The end point the lower right corner. When the row and line counter values of the output interface are equal to the action point values, the output becomes HIGH or LOW according to the set-up. The possible actions for the start point are set or toggle and for the end point reset or toggle. The output signal can be inverted additionally. Two modes are available: frame or line based. In frame based mode the signal only changes in the upper, left and the lower, right corner of each frame. In line based mode the signal changes every line at the beginning and at the end of the operation window. It is also possible to use just one action point, e.g. to toggle the output each line or just once in a frame. To disable an action point a logic 0 has to be programmed to the y-value. CSG0 and CSG1 are driven by two separate signal generators (CSG0A or CSG0B and CSG1A or CSG1B respectively) allowing a more complex signal to be generated.
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1,1 a action point in frame and line mode additional action points in line mode in line mode the signal will be repeated in every line in the operation window
operation window b last_line main frame
MHC235
blank_line_length
Fig.28 Output frame set-up.
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Product specification
XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
start_point (a) 1,1 1,1
start_point (a)
last_line end_point (b) line based operation window
last_line end_point (b) frame based
MHC236
Fig.29 Examples for signal generator outputs.
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t 1,1 hs vs start_point (a) hs hs line based hs hs hs end_point (b) hs vs
t 1,1 hs vs start_point (a) hs hs frame based hs hs hs end_point (b)
MHC237
hs vs
Fig.30 Examples for signal generator outputs.
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XGA analog input flat panel controller
7.16.5 SPECIAL FEATURES AND CSG GROUPS
SAA6713AH
7.16.5.3 CSG6 and CSG7
7.16.5.1
CSG0 and CSG1
No special or additional features. Two action points.
These CSGs are two CSGs with one output (see Fig.31). They are splitted in CSGXa and CSGXb. The a and b part are equal and the programming is as two separated CSGs. So one can generate signals with four events each line/frame.
7.16.5.4
CSG8 and CSG9
7.16.5.2
CSG2 to CSG5
These CSGs have an additional action point. The signal can be set, reset or toggled in this point. The execution of action point 0 can be depressed only in line mode for every second line. The execution of action point 1 and 2 is not influenced by skip_mode.
Normal CSGs with two action points. Additionally, CSG2 plus CSG3 and CSG4 plus CSG5 can cooperate like CSG0/1 a/b on outputs CSG3 and CSG5.
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t 1,1 hs vs set reset hs hs hs hs hs hs vs
t 1,1 hs vs hs toggle hs line based hs hs hs hs vs
t 1,1 hs vs hs hs frame based hs hs hs hs vs
MHC238
Fig.31 Examples for CSG0/1 outputs.
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7.16.6 TRANSITION MINIMIZING
SAA6713AH
Because there is no previous data for the first data in every column (horizontal period), the above noted toggle operations for INVA and INVB, as well as the data inversion operations are not performed. In the event of first data output of every column, INVA and INVB are set to LOW, and data is not inverted.
The transition minimizing programming is done in the OI_CTRL0 register in the OIF. This section describes how the OIF pixel input operates with INVA and INVB outputs for various values of ivsl0 and ivsl1 (register OI_CTRL0). All modes are designed for double pixel handling.
7.16.6.1
Bit ivsl0 = 1 and bit ivsl1 = 0
7.16.6.3
Bit ivsl0 = 0 and bit ivsl1 = 0
INVA operates with input pixel 0 (means the first of a couple). This inversion operation considers a total of 18 bits: the 6 high order bits of each colour component of input pixel 0 (R2 to R7, G2 to G7 and B2 to B7). The input data of time (n - 1) is compared to the data at time n. If 10 or more bits within the 18 bits have changed from LOW to HIGH or from HIGH to LOW, then INVA toggles between HIGH and LOW: if INVA was HIGH at (n - 1) it goes LOW, and if it was LOW at (n - 1), it toggles HIGH. If 9 or fewer bits within the 18 bits have changed from HIGH to LOW or from LOW to HIGH, then INVA does not toggle. When INVA is HIGH, all bits (24 bits) of pixel 0 to output (means data before `data to output mapping') are inverted. INVB operates with input pixel 1 (means the second of a couple). This inversion operation considers a total of 18 bits: the 6 high order bits of each colour component of input pixel 1 (R2 to R7, G2 to G7 and B2 to B7). The input data of time (n - 1) is compared to the data at time n. If 10 or more bits within the 18 bits have changed from LOW to HIGH or from HIGH to LOW, then INVB toggles between HIGH and LOW: if INVB was HIGH at (n - 1), it goes LOW, and if it was LOW at (n - 1), it toggles HIGH. If 9 or fewer bits within the 18 bits have changed from HIGH to LOW or from LOW to HIGH, then INVB does not toggle. When INVB is HIGH, all bits (24 bits) of pixel 1 to output are output inverted.
For input pixel, data inversion is similar to when ivsl0 = 1, ivsl1 = 0, with input pixel 0 and 1 being separated, and the outputs being driven according to the results of calculations. For INVA and INVB signals, the calculations are similar to when ivsl0 = 1, ivsl1 = 0, but the INVA and INVB outputs are driven as logical opposites.
7.16.6.4
Bit ivsl0 = 0 and bit ivsl1 = 1
The INVA and INVB signals are always driven LOW and data inversion operations are not performed. 7.16.7 BACKGROUND AND EMERGENCY FRAME GENERATOR
The output interface includes a simple frame generator. It may be useful when the front-end receives no signal, so no front-end clock is available. The generated frame has the same dimensions as the picture area. The frame colour is programmable (OI_FCx). The on screen display is still working. The generator may be switched on via the OI_FC_EN register.
7.16.6.2
Bit ivsl0 = 1 and bit ivsl1 = 1
INVA and INVB both operate with input pixel 0 and 1.This inversion operation considers a total of 36 bits, the 6 high order bits of each colour component of pixel 0 and 1 (0R2 to 0R7, 0G2 to 0G7, 0B2 to 0B7, 1R2 to 1R7, 1G2 to 1G7 and 1B2 to 1B7). The input data of time (n - 1) is compared to the data at time n. If 19 or more bits within the 36 bits have changed from LOW to HIGH or from HIGH to LOW, then both INVA and INVB toggle between HIGH and LOW. When INVA and INVB are HIGH at (n - 1), they go LOW, and when they are LOW at (n - 1), they toggle HIGH. If 18 or fewer bits within the 36 bits have changed from HIGH to LOW or from LOW to HIGH, then INVA and INVB do not toggle. When INVA and INVB are both HIGH, all bits (48 bits) are inverted.
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7.16.8 GLOBAL CONTROL
SAA6713AH
The output interface has four global modes, which can be programmed with bits OI_enable, power_down and blank_mode (register OI_CTRL0) according to Table 54. The blank colour is programmable via bits blank_colour_red, blank_colour_green and blank_colour_blue. Table 54 Global modes; note 1 OI_ enable 1 X 0 1 Note 1. X = don't care. 7.16.9 PANEL CLOCK 7.16.10 HOW TO START THE OUTPUT INTERFACE Table 56 Starting output interface STEP 1 2 3 4 5 ACTION set-up frame geometry set-up signal generators set-up wait column and wait mode set-up PCLK and pixel mode enable output interface power_ down 0 1 0 0 blank_ mode 1 X X 0 MODE blank Power-down disable normal ACTION all colours replaced by blank colour values all registers set to default, like soft reset; all outputs LOW all outputs reset but incoming data queued to trash normal operation
The output interface can handle single and double pixel mode (bit double_pixel in register OI_CTRL1). In single pixel mode one pixel (24 bits) is available each cycle at the output ports. The panel clock PCLK is the same as the back-end clock. In double pixel mode 2 pixels (48 bits) are available at the output ports. The PCLK in double pixel mode changes every second cycle of the back-end clock. The panel clock polarity can be inverted by setting PCLK_pol of register OI_CTRL1 to logic 1. At the beginning of each frame the PCLK is synced again. It is very important that the number of pixels in a double pixel frame is even. The horizontal sync signal of the VGA video input source may be used as a reference clock for the panel PLL (see Table 55). This allows more stable locking of the panel timing to the source timing. In this mode the PLL will be `coasted' during vertical sync when a composite sync or sync-on-green is enabled (iif_cs_sog_en = 1). Table 55 Panel PLL pll_src 0 1 HS_PLL FUNCTION pre-divided clock
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XGA analog input flat panel controller
7.16.11 PROGRAMMABLE OUTPUT DRIVE STRENGTH For all data and control signals of the output interface (PA[7:0], PB[7:0], PC[7:0], PD[7:0], PE[7:0], PF[7:0], CSG[9:0], INVA, INVB, OUTEN and PWM) a programmable output drive strength up to 15 mA is provided (in 8 steps and starting at 2.9 mA); see Table 57. For the PCLK output, a programmable output drive up to 30 mA is provided (in 8 steps and starting at 5.8 mA); see Table 57. Individual drive strength programming is possible for each 8-bit group of data signals (see Table 58). The drive strength of control and clock signals are programmable individually. This is necessary to drive the multiple source and gate drivers directly.
SAA6713AH
Table 57 Programmable drive strength DATA AND CONTROL OUTPUTS (mA) 2.9 3.4 4 5 6 8 11 15 PCLK OUTPUT (mA) 5.8 6.8 8 10 12 16 22 30
DS2
DS1
DS0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Table 58 Output interface drive strength BIT pin_drv_inva[2:0] pin_drv_invb[2:0] pin_drv_pa[2:0] pin_drv_pb[2:0] pin_drv_pc[2:0] pin_drv_pd[2:0] pin_drv_pe[2:0] pin_drv_pf[2:0] pin_drv_csg0[2:0] pin_drv_csg1[2:0] pin_drv_csg2[2:0] pin_drv_csg3[2:0] pin_drv_csg4[2:0] pin_drv_csg5[2:0] pin_drv_csg6[2:0] pin_drv_csg7[2:0] pin_drv_csg8[2:0] pin_drv_csg9[2:0] pin_drv_pwm[2:0] pin_drv_outen[2:0] pin_drv_pclk[2:0] DESCRIPTION output drive strength for INVA output drive strength for INVB output drive strength for PA output drive strength for PB output drive strength for PC output drive strength for PD output drive strength for PE output drive strength for PF output drive strength for CSG0 output drive strength for CSG1 output drive strength for CSG2 output drive strength for CSG3 output drive strength for CSG4 output drive strength for CSG5 output drive strength for CSG6 output drive strength for CSG7 output drive strength for CSG8 output drive strength for CSG9 output drive strength for PWM output drive strength for OUTEN output drive strength for PCLK from 5.8 mA (reset) to 30 mA; see Table 57 REMARK from 2.9 mA (reset) to 15 mA; see Table 57
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XGA analog input flat panel controller
7.16.12 ADJUSTABLE OUTPUT DELAYS
SAA6713AH
Every output pin, except pin PWM, can be delayed. The delay increment is 0.36 ns. The programming value is 5-bit wide (see Table 59). Table 59 Data to output mapping REGISTER OI_INVA_DEL OI_INVB_DEL OI_PAD OI_PBD OI_PCD OI_PDD OI_PED OI_PFD OI_CTRL1 OI_G0BD OI_G1BD OI_G2D OI_G3D OI_G4D OI_G5D OI_G6D OI_G7D OI_G8D OI_G9D 7.16.13 PULSE WIDTH MODULATION A pulse width modulated signal can be generated for brightness control of the panel. The pulse width and the pre-divider value can be programmed. The PWM can be synced with the h-gate. The logical polarity can be inverted. The PWM runs with the system clock and can be divided by the pre-divider. A period depends on 256 cycles. The configuration registers for the PWM are OI_PWM0 and OI_PWM1. 7.16.14 RESET BEHAVIOUR A hardware reset forces all true bidirectional pins (PAx, PBx, PCx, VCLK, VSYNC and SDA) to input. Their output functionality must be explicitly invoked by software. CSG2/A0 and CSG4/A1 are input during the hardware reset for latching in the configuration data and switched to output immediately after hardware reset. 2004 Apr 05 85 BIT inversion_A_pin_delay[4:0] inversion_B_pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] PCLK_pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] pin_delay[4:0] 8 INVA INVB PA PB PC PD PE PF PCLK CSG0 CSG1 CSG2 CSG3 CSG4 CSG5 CSG6 CSG7 CSG8 CSG9 BOUNDARY SCAN TEST OUTPUT
The SAA6713AH has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA6713AH follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are: Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 60). Details about the JTAG BST-TEST can be found in the specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA6713AH is available on request.
Philips Semiconductors
Product specification
XGA analog input flat panel controller
8.1 Initialization of boundary scan circuit
SAA6713AH
When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.32.
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in the functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting pin TRST to LOW. 8.2 Device identification codes
A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. Table 60 BST instructions supported by the SAA6713AH INSTRUCTION BYPASS EXTEST SAMPLE DESCRIPTION This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. This optional instruction allows testing of the internal logic (no customer support available). This private instruction allows testing by the manufacturer (no customer support available).
CLAMP IDCODE INTEST USER1
handbook, full pagewidth
MSB 31 TDI 28 27 0110 0111 0001 0011 16-bit part number 12 11 0000 0010 101 11-bit manufacturer identification
LSB 1 0 1 TDO
nnnn 4-bit version code
MHC239
Fig.32 32 bits of identification code.
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XGA analog input flat panel controller
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134) SYMBOL VDDD(IC) VDDA PARAMETER digital supply voltage for internal core on pins VDDD(IC1) to VDDD(IC9) analog supply voltage on pins VDDA(R), VDDA(G), VDDA(B), VDDA(ADC)(R), VDDA(ADC)(G) and VDDA(ADC)(B) supply voltage for PLL on pins VDD(PLL)(P), VDDD(PLL)(S) and VDDA(PLL)(S) analog supply voltage for input buffer on pin VDDA(IB) external digital pad supply voltage for pins VDDD(EP1) to VDDD(EP10) external analog pad supply voltage for pin VDDA(EP) voltage on digital input pins SDA and SCL (5 V tolerant) digital input pins analog input and output pins Ptot Tstg Tj Tamb Vesd total power dissipation storage temperature junction temperature ambient temperature electrostatic discharge voltage note 2 note 3 Notes note 1 -0.5 -0.5 -0.5 - -25 - 0 -1500 -150 CONDITIONS MIN. -0.5 0
SAA6713AH
MAX. +3.3 2.8
UNIT V V
VDD(PLL), VDDD(PLL), VDDA(PLL), VDDA(IB) VDDD(EP) VDDA(EP) Vn
0
2.8
V
0 -0.5 0
3.3 +4.2 3.6
V V V
+5.8 VDDD(EP) + 0.5 VDDA + 0.5 1.7 +150 125 70 +2000 +150
V V V W C C C V V
1. May not exceed 4.2 V; including outputs in 3-state mode; only when supply voltages are present. 2. Human body model: C = 100 pF; R = 1.5 k. 3. Machine model: C = 200 pF; L = 0.75 H; R = 0 . 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 26 UNIT K/W
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XGA analog input flat panel controller
11 CHARACTERISTICS Tamb = 25 C; unless otherwise specified. SYMBOL Supplies DIGITAL SUPPLY FOR INTERNAL CORE: PINS VDDD(IC1) TO VDDD(IC9) VDDD(IC) IDDD(IC) PDDD(IC) supply voltage supply current power dissipation note 1 note 1 2.3 - - 2.5 90 225 PARAMETER CONDITIONS MIN. TYP.
SAA6713AH
MAX.
UNIT
2.7 - -
V mA mW
ANALOG SUPPLY FOR COLOUR CHANNELS AND ADCS: PINS VDDA(R), VDDA(G), VDDA(B), VDDA(ADC)(R), VDDA(ADC)(G) AND VDDA(ADC)(B) VDDA IDDA PDDA VDD(PLL) IDD(PLL) PDD(PLL) VDDA(IB) IDDA(IB) PDDA(IB) VDDD(EP) IDDD(EP) PDDD(EP) VDDA(EP) IDDA(EP) PDDA(EP) supply voltage supply current power dissipation note 1 note 1 2.3 - - 2.3 note 1 note 1 - - 2.7 note 1 note 1 - - 3.0 note 1 note 1 - - 3.0 note 1 note 1 - - 2.5 200 500 2.7 - - 2.7 - - 3.3 - - 3.6 - - 3.6 - - V mA mW
SUPPLY FOR PLL: PINS VDD(PLL)(P), VDDA(PLL)(S) AND VDDD(PLL)(S) supply voltage supply current power dissipation 2.5 5 13 V mA mW
ANALOG SUPPLY FOR INPUT BUFFER: PIN VDDA(IB) supply voltage supply current power dissipation 3.0 2 6 V mA mW
DIGITAL SUPPLY FOR PADS: PINS VDDD(EP1) TO VDDD(EP10) supply voltage supply current power dissipation 3.3 50 165 V mA mW
ANALOG SUPPLY FOR PAD: PIN VDDA(EP) supply voltage supply current power dissipation 3.3 1 3 V mA mW
Analog front-end inputs ANALOG VIDEO INPUTS: PINS RIN, GIN AND BIN Vi(p-p) Ci Vi(p-p) input voltage (peak-to-peak value) input capacitance note 2 0.2 - 0.1 - 850 - 0.5 - 0.4 V fF
SYNC-ON-GREEN SLICER INPUT: PIN SOGIN input voltage (peak-to-peak value) V
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XGA analog input flat panel controller
SAA6713AH
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - 8 0.8 1.6 7
MAX.
UNIT
ANALOG-TO-DIGITAL CONVERTER fpixel N LEdc(i) LEdc(d) ENOB sample clock of ADC resolution of ADC DC integral linearity error DC differential linearity error effective number of bits fpixel = 110 MHz 25 - - - 6.6 - 110 - - - - - MHz bits LSB LSB bits
CONTROL LOOPS FOR CONTRAST AND BRIGHTNESS M matching of contrast and clamp settings among the three channels bandwidth of contrast and clamp loops required width of clamp pulse required width of gain control pulse 1 %
Bloop Nclamp Ngainc
- 40 96
500 - -
- - -
Hz pixels pixels
Digital inputs CLOCK, RESET AND BST INPUTS: PINS CLK, RST, TCK, TDI, TMS AND TRST VIL VIH IIL IIH Ci VIL VIH IIL IIH Ci LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance 0 1.7 - - - 0 2 - - - - - - - - - - - - - 0.7 VDDD(EP) 1 1 8 V V A A pF
HORIZONTAL SYNC INPUT: PIN HSYNC (5 V TOLERANT) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance 0.8 5.5 1 1 8 V V A A pF
Output pins DATA PORTS AND PANEL CONTROL SIGNALS: PINS PD0 TO PD7, PE0 TO PE7, PF0 TO PF7, CSG0, CSG1, CSG3, CSG5 TO CSG9, INVA, INVB, PCLK, PWM AND OUTEN VOL VOH Ipu LOW-level output voltage HIGH-level output voltage pull-up current IOL = 16 mA IOH = -16 mA Vi = 0 - VDDD(EP) - 0.4 -23 - - -50 0 0.4 - -65 - V V A A
VDD < Vi - -
0.4 -
V V
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Product specification
XGA analog input flat panel controller
SAA6713AH
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input or output pins DATA PORTS, PANEL CONTROL SIGNALS, SAMPLE CLOCK AND VERTICAL SYNC PULSES: PINS PA0 TO PA7, PB0 TO PB7, PC0 TO PC7, CSG2/A0 AND CSG4/A1 VIL VIH VOL VOH Ipu LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage pull-up current IOL = 16 mA IOH = -16 mA Vi = 0 0 2.0 0 VDDD(EP) - 0.4 -23 - - - - -50 0 - - - - - 50 - - - - - - - 0.8 3.6 0.4 VDDD(EP) -65 - 8 V V V V A A pF
VDD < Vi 0.8 5.5 0.4 VDDD(EP) 53 8
V V V V A pF
SAMPLE CLOCK: PIN VCLK LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage 3-state output leakage current input capacitance 0.7 VDDD(EP) 0.4 VDDD(EP) 1 8 V V V V A pF
I2C-bus interface CLOCK INPUT: PIN SCL VIL VIH Vhys IIL IIH Ci VIL VIH Vhys VOL LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level input current HIGH-level input current input capacitance 5 V tolerant 0 2.0 0.3 - - - 0 5 V tolerant IOL = 4 mA 2.0 0.3 0 - - - - - - - - - - 0.8 5.5 - 1 1 8 V V V A A pF
DATA INPUT AND OUTPUT: PIN SDA LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage 0.8 5.5 - 0.4 V V V V
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XGA analog input flat panel controller
Notes 1. 1024 x 768 at 60 Hz with input pattern Grill_33. 2. Pin connected to video source via a 6 dB/75 attenuator. 3. Leakage current due to external voltage higher than internal VDD. 4. Minimum value for Vi = 4.5 V; maximum value for Vi = 5.5 V. 12 TIMING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - 500 TYP.
SAA6713AH
MAX.
UNIT
System clock input at pin CLK Tcy Tcy tsu th tVSYNC tHSYNC Tcy tsu th Tcy tout1 tout2 tdel system clock cycle time 20 41.66 - - - - - - - - 40 +0.2 -0.8 800 ns
Analog video interface; see Fig.33 analog video clock cycle time video data set-up time video data hold time vertical sync length horizontal sync length 9.1 4 3 2/fVCLK 2/fVCLK 9.1 0 5 ns ns ns ns ns
Parallel video interface; see Fig.34 parallel video clock cycle time video data set-up time video data hold time ns ns ns
Panel interface; see Fig.35 panel clock cycle time undelayed PCLK to output delay time; single pixel mode undelayed PCLK to output delay time; double pixel mode output delay increment CL = 15 pF CL = 15 pF 15.4 -2.5 -3.5 200 ns ns ns ps
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XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
Tcy
VCLK
t su th HSYNC, VSYNC
MHC240
Fig.33 Analog video interface timing.
handbook, full pagewidth
Tcy
VCLK
t su th PA, PB, PC
MHC241
Fig.34 Parallel video interface timing.
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XGA analog input flat panel controller
SAA6713AH
handbook, full pagewidth
Tcy
PCLK
t out1 PA, PB, PC, PD, PE, PF, INVA, INVB, CSG undelayed, single pixel mode t out2 PA, PB, PC, PD, PE, PF, INVA, INVB, CSG undelayed, double pixel mode t out + n x t del
delayed
MHC242
Fig.35 Panel interface timing.
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XGA analog input flat panel controller
13 APPLICATION INFORMATION
SAA6713AH
handbook, full pagewidth
VGA PORT
SAA6713AH
PANEL CONNECTOR
I2C-bus
EEPROM
MICROCONTROLLER USB
MHC281
Fig.36 Application board block diagram.
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XGA analog input flat panel controller
14 PACKAGE OUTLINE
QFP160: plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height
SAA6713AH
SOT322-2
c
y X
A 120 121 81 80 ZE
e E HE A A2 A1 (A 3) Lp L detail X 41 1 bp D HD wM ZD B vM B 40 vM A
wM bp pin 1 index 160
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.07 A1 0.50 0.25 A2 3.6 3.2 A3 0.25 bp 0.38 0.22 c 0.23 0.13 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.65 HD HE L 1.6 Lp 1.03 0.73 v 0.3 w 0.13 y 0.1 Z D(1) Z E (1) 1.5 1.1 1.5 1.1 7 o 0
o
31.45 31.45 30.95 30.95
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT322-2 REFERENCES IEC 135E12 JEDEC MS-022 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
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15 SOLDERING 15.1 Introduction to soldering surface mount packages
SAA6713AH
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 220 C (SnPb process) or below 245 C (Pb-free process) - for all BGA and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 Wave soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
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XGA analog input flat panel controller
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP PMFP(8) Notes not suitable not suitable(4)
SAA6713AH
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable not suitable
suitable not recommended(7) not suitable
not recommended(5)(6) suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Hot bar or manual soldering is suitable for PMFP packages.
2004 Apr 05
97
Philips Semiconductors
Product specification
XGA analog input flat panel controller
16 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
SAA6713AH
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Apr 05
98
Philips Semiconductors
Product specification
XGA analog input flat panel controller
19 PURCHASE OF PHILIPS I2C COMPONENTS
SAA6713AH
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2004 Apr 05
99
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R21/02/pp100
Date of release: 2004
Apr 05
Document order number:
9397 750 12102

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